| 2006 |
|---|
| 9 | EE | Shekhar Y. Borkar,
Robert W. Brodersen,
Jue-Hsien Chern,
Eric Naviasky,
D. Saias,
Charles Sodini:
Tomorrow's analog: just dead or just different?
DAC 2006: 709-710 |
| 2005 |
|---|
| 8 | EE | Jue-Hsien Chern:
Challenges of analog/mixed-signal SoC design and verification.
ISPD 2005: 102 |
| 1993 |
|---|
| 7 | EE | Mi-Chang Chang,
Jue-Hsien Chern,
Ping Yang:
An accurate grid local truncation error for device simulation.
ICCAD 1993: 275-282 |
| 6 | | Mi-Chang Chang,
Jue-Hsien Chern,
Ping Yang:
Efficient and Robust Path Tracing Algorithm for DC Convergence Problem.
ISCAS 1993: 1635-1638 |
| 5 | EE | Kartikeya Mayaram,
Jue-Hsien Chern,
Ping Yang:
Algorithms for transient three-dimensional mixed-level circuit and device simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(11): 1726-1733 (1993) |
| 1991 |
|---|
| 4 | | Kartikeya Mayaram,
Ping Yang,
Jue-Hsien Chern:
Transient Three-Dimensional Mixed-Level Circuit and Device Simulation: Algorithms and Applications.
ICCAD 1991: 112-115 |
| 1990 |
|---|
| 3 | | Kartikeya Mayaram,
Ping Yang,
Jue-Hsien Chern,
Richard Burch,
Lawrence A. Arledge Jr.,
Paul F. Cox:
A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device Simulations.
ICCAD 1990: 446-449 |
| 1989 |
|---|
| 2 | EE | Jue-Hsien Chern,
John T. Maeda,
Lawrence A. Arledge Jr.,
Ping Yang:
SIERRA: a 3-D device simulator for reliability modeling.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(5): 516-527 (1989) |
| 1987 |
|---|
| 1 | EE | K. C.-K. Weng,
Ping Yang,
Jue-Hsien Chern:
A Predictor/CAD Model for Buried-Channel MOS Transistors.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(1): 4-16 (1987) |
