2001 |
9 | EE | Jun Cao,
Belle W. Y. Wei,
Jie Cheng:
High-Performance Architectures for Elementary Function Generation.
IEEE Symposium on Computer Arithmetic 2001: 136- |
1997 |
8 | EE | Jun Cao,
Belle W. Y. Wei:
High-Performance Hardware for Function Generation.
IEEE Symposium on Computer Arithmetic 1997: 184- |
1995 |
7 | EE | Belle W. Y. Wei,
He Du,
Honglu Chen:
A complex-number multiplier using radix-4 digits.
IEEE Symposium on Computer Arithmetic 1995: 84- |
1994 |
6 | | Belle W. Y. Wei,
Teresa H. Y. Meng:
A Programmable Parallel Huffman Decoder.
ICIP (3) 1994: 668-671 |
5 | EE | K. Tsang,
Belle W. Y. Wei:
A VLSI architecture for a real-time code book generator and encoder of a vector quantizer.
IEEE Trans. VLSI Syst. 2(3): 360-364 (1994) |
1993 |
4 | | Belle W. Y. Wei,
Richard Tarver,
Jong-Seop Kim,
Kevin Ng:
A Single Chip Lempel-Ziv Data Compressor.
ISCAS 1993: 1953-1955 |
1991 |
3 | EE | Xiaoping Huang,
Belle W. Y. Wei,
Honglu Chen,
Yuhai H. Mao:
High-performance VLSI multiplier with a new redundant binary coding.
VLSI Signal Processing 3(4): 283-291 (1991) |
1990 |
2 | | Belle W. Y. Wei,
Clark D. Thompson:
Area-Time Optimal Adder Design.
IEEE Trans. Computers 39(5): 666-675 (1990) |
1989 |
1 | EE | Clark D. Thomborson,
Belle W. Y. Wei:
Systolic Implementations of a Move-to-Front Text Compressor.
SPAA 1989: 283-290 |