| 1996 |
|---|
| 5 | EE | S. C. Prasad,
Kaushik Roy:
Transistor reordering for power minimization under delay constraint.
ACM Trans. Design Autom. Electr. Syst. 1(2): 280-300 (1996) |
| 1995 |
|---|
| 4 | EE | S. C. Prasad,
Kaushik Roy:
Circuit optimization for minimisation of power consumption under delay constraint.
VLSI Design 1995: 305-309 |
| 1994 |
|---|
| 3 | EE | S. C. Prasad,
P. Anirudhan,
Patrick W. Bosshart:
A System for Incremental Synthesis to Gate-Level and Reoptimization Following RTL Design Changes.
DAC 1994: 441-446 |
| 1993 |
|---|
| 2 | | S. C. Prasad,
P. W. Kollaritsch,
P. Anirudhan,
D. K. Hwang,
S. Lusky,
R. Farrow:
Efficient Floorplan Enumeration Using Dynamic Programming.
ISCAS 1993: 1766-1769 |
| 1 | EE | Kaushik Roy,
S. C. Prasad:
Circuit activity based logic synthesis for low power reliable operations.
IEEE Trans. VLSI Syst. 1(4): 503-513 (1993) |
