| |
| 1997 | ||
|---|---|---|
| 3 | EE | An-Nan Suen, Jhing-Fa Wang, Jia-Lang Lin: VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements. Integration 24(1): 79-97 (1997) |
| 1995 | ||
| 2 | An-Nan Suen, Jhing-Fa Wang, Yuen-Lin Chiang: A Cepstrum Chip: Architecture and Implementation. ISCAS 1995: 1428-1431 | |
| 1993 | ||
| 1 | Ming-Hwa Sheu, Jau-Yien Lee, Jhing-Fa Wang, An-Nan Suen, Lian-Ying Liu: A High Throughput-Rate Architecture for 8*8 2-D DCT. ISCAS 1993: 1578-1590 | |
| 1 | Yuen-Lin Chiang | [2] |
| 2 | Jau-Yien Lee | [1] |
| 3 | Jia-Lang Lin | [3] |
| 4 | Lian-Ying Liu | [1] |
| 5 | Ming-Hwa Sheu | [1] |
| 6 | Jhing-Fa Wang | [1] [2] [3] |