Perng-Shyong Lin

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1993

2 Perng-Shyong Lin, Charles A. Zukowski: Analysis and Control of Timing Jitter in Digital Logic Arising from Noise Voltage Sources. ICCD 1993: 352-356

1 Perng-Shyong Lin, Charles A. Zukowski: Jitter Due to Signal History in Digital Logic Circuits and Its Control Strategies. ISCAS 1993: 2114-2117

1993
2		Perng-Shyong Lin, Charles A. Zukowski: Analysis and Control of Timing Jitter in Digital Logic Arising from Noise Voltage Sources. ICCD 1993: 352-356
1		Perng-Shyong Lin, Charles A. Zukowski: Jitter Due to Signal History in Digital Logic Circuits and Its Control Strategies. ISCAS 1993: 2114-2117

Coauthor Index

1 Charles A. Zukowski [1] [2]