| 2009 |
|---|
| 40 | EE | Fadi Riad Shahroury,
Chung-Yu Wu:
A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback matching network.
Integration 42(1): 83-88 (2009) |
| 2008 |
|---|
| 39 | EE | Wen-Chieh Wang,
Chang-Ping Liao,
Yi-Kai Lo,
Zue-Der Huang,
Fadi Riad Shahroury,
Chung-Yu Wu:
The design of integrated 3-GHz to 11-GHz CMOS transmitter for full-band ultra-wideband (UWB) applications.
ISCAS 2008: 2709-2712 |
| 2007 |
|---|
| 38 | | Ming-Jong Tsai,
Chao-Hsiang Feng,
Chung-Yu Wu,
Chang-Jung Juan:
An efficient Compensation Method for Improving Luminance Uniformity of Organic Light Emitting Diode Panels.
CSC 2007: 177-182 |
| 37 | EE | Chung-Yu Wu,
Shun-Wei Hsu,
Wen-Chieh Wang:
A 24-GHz CMOS Current-Mode Power Amplifier with High PAE and Output Power.
ISCAS 2007: 2866-2869 |
| 36 | EE | Chung-Yu Wu,
Chien-Ta Huang:
A CMOS Expansion/Contraction Motion Sensor with a Retinal Processing Circuit for Z-motion Detection Applications.
ISCAS 2007: 3087-3090 |
| 2005 |
|---|
| 35 | EE | Chung-Yu Wu,
Chi-Yao Yu:
A 0.8 V 5.9 GHz wide tuning range CMOS VCO using inversion-mode bandswitching varactors.
ISCAS (5) 2005: 5079-5082 |
| 2004 |
|---|
| 34 | | Chung-Yu Wu,
Felice Cheng,
Cheng-Ta Chiang,
Po-Kang Lin:
A low-power implantable Pseudo-BJT-based silicon retina with solar cells for artificial retinal prostheses.
ISCAS (4) 2004: 37-40 |
| 2003 |
|---|
| 33 | EE | Yu-Chuan Shih,
Chung-Yu Wu:
An optimized CMOS pseudo-active-pixel-sensor structure for low-dark-current imager applications.
ISCAS (1) 2003: 809-812 |
| 2002 |
|---|
| 32 | EE | Chung-Yun Chou,
Chung-Yu Wu:
The design of a new wideband and low-power CMOS active polyphase filter for low-IF receiver applications.
APCCAS (1) 2002: 241-244 |
| 31 | EE | Hong-Sing Kao,
Chung-Yu Wu:
An improved low-power CMOS direct-conversion transmitter for GHz wireless communication applications.
APCCAS (1) 2002: 5-8 |
| 30 | EE | Chung-Yu Wu,
Wen-Chieh Wang,
Tzung-Ming Chen:
A new high-performance CMOS GHz power amplifier design with common-mode signal cancellation technique.
APCCAS (2) 2002: 395-398 |
| 29 | EE | Chung-Yu Wu,
Jui-Lin Lai:
Improvement of pattern learning and recognition capability in ratio-memory cellular neural networks with non-discrete-type Hebbian learning algorithm.
ISCAS (1) 2002: 629-632 |
| 28 | EE | Yu-Yee Liow,
Chung-Yu Wu:
The design of high-speed pipelined analog-to-digital converters using voltage-mode sampling and current mode processing techniques.
ISCAS (3) 2002: 117-120 |
| 2001 |
|---|
| 27 | EE | Chung-Yu Wu,
Chung-Yun Chou:
The design of a CMOS IF bandpass amplifier with low sensitivity to process and temperature variations.
ISCAS (1) 2001: 121-124 |
| 1999 |
|---|
| 26 | EE | Chung-Yu Wu,
Yu-Yee Liow:
A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMs.
ISCAS (1) 1999: 47-50 |
| 25 | EE | Yu-Chuan Shih,
Chung-Yu Wu:
The design of high-performance 128×128 CMOS image sensors using new current-readout techniques.
ISCAS (5) 1999: 168-171 |
| 24 | EE | Wen-Cheng Yen,
Chung-Yu Wu:
A new compact neuron-bipolar cellular neural network structure with adjustable neighborhood layers and high integration level.
ISCAS (6) 1999: 505-508 |
| 23 | EE | Chung-Yu Wu,
Hsin-Chin Jiang:
An improved BJT-based silicon retina with tunable image smoothing capability.
IEEE Trans. VLSI Syst. 7(2): 241-248 (1999) |
| 1996 |
|---|
| 22 | EE | Ming-Dou Ker,
Chung-Yu Wu,
Tao Cheng,
Hun-Hsien Chang:
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC.
IEEE Trans. VLSI Syst. 4(3): 307-321 (1996) |
| 1995 |
|---|
| 21 | | Chung-Yu Wu,
Wei-Shinn Wey,
Tsai-Chung Yu:
A 1.5V CMOS Balanced Differential Switched-Capacitor Filter with Internal Clock Boosters.
ISCAS 1995: 1025-1028 |
| 20 | | Hong-Yi Huang,
Jinn-Shyan Wang,
Yuan-Hua Chu,
Tain-Shun Wu,
Kuo-Hsing Cheng,
Chung-Yu Wu:
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.
ISCAS 1995: 1572-1575 |
| 19 | | Jeng-Feng Lan,
Chung-Yu Wu:
CMOS Current-Mode Outstar Neural Networks with Long-Period Analog Ratio Memory.
ISCAS 1995: 1676-1679 |
| 18 | | Chung-Yu Wu,
Shuo-Yuan Hsiao,
Ron-Yi Liu:
A 3-V 1-GHz Low-Noise Bandpass Amplifier.
ISCAS 1995: 1964-1967 |
| 17 | | Chung-Yu Wu,
Jr-Houng Lu,
Kuo-Hsing Cheng:
A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage Applications.
ISCAS 1995: 25-28 |
| 16 | | Chung-Yu Wu,
Heng-Shou Hsu:
The Design of New Low-Voltage CMOS VHF Continuous-Time Lowpass Biquaud Filters.
ISCAS 1995: 295-298 |
| 15 | | Chih-Cheng Chen,
Chung-Yu Wu,
Jyh-Jer Cho:
A 1.5 V CMOS Current-Mode Cyclic Analog-to-Digital Converter with Digital Error Correction.
ISCAS 1995: 537-540 |
| 14 | | Ming-Dou Ker,
Chung-Yu Wu,
Hun-Hsien Chang,
Tao Cheng,
Tain-Shun Wu:
Complementary-LVTSCR ESD Protection Scheme for Submicron CMOS IC's.
ISCAS 1995: 833-836 |
| 13 | EE | Chung-Yu Wu,
Ron-Yi Liu:
CMOS current-mode implementation of spatiotemporal probabilistic neural networks for speech recognition.
VLSI Signal Processing 10(1): 67-84 (1995) |
| 1994 |
|---|
| 12 | | Hong-Yi Huang,
Chung-Yu Wu:
New CMOS Differential Logic Circuits for True-Single-Phase Pipelined Systems.
ISCAS 1994: 15-18 |
| 11 | | Yuh-Kuang Tseng,
Kuo-Hsing Cheng,
Chung-Yu Wu:
Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit.
ISCAS 1994: 23-26 |
| 10 | | Shu-Yuan Chin,
Chung-Yu Wu:
An Alorithmic Analog-to-Digital Converter with low Ratio-and Gain-Sensitivities and 4N-Clock Conversion Cycle.
ISCAS 1994: 325-328 |
| 9 | | Liang-Hung Lu,
Chung-Yu Wu:
The Design of the CMOS Current-Mode General-Purpose Analog Processor.
ISCAS 1994: 549-552 |
| 8 | | Ping-Hsing Lu,
Chung-Yu Wu,
Ming-Kai Tsai:
VHF/UHF High-Q Bandpass Tunable Filters Design Using CMOS Inverter-Based Transresistnace Amplifiers.
ISCAS 1994: 649-652 |
| 7 | | Chung-Yu Wu,
Heng-Shou Hsu:
The Continuous-Time VHF Lowpass Filter Design Using Finite-Gain Current and Voltage Amplifiers and Special Q-Enhancement Circuit.
ISCAS 1994: 771-774 |
| 1993 |
|---|
| 6 | | Shu-Yuan Chin,
Chung-Yu Wu:
A Ratio-independent and Gain-insensitive Algorithmic Analog-to-digital Converter.
ISCAS 1993: 1200-1203 |
| 5 | | Ying-Hwi Chang,
Chung-Yu Wu,
Tsai-Chung Yu:
Chopper-stabilized Sigma-delta Modulator.
ISCAS 1993: 1286-1289 |
| 4 | | Hong-Yi Huang,
Chung-Yu Wu:
Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications.
ISCAS 1993: 1905-1908 |
| 3 | | Ping-Hsing Lu,
Chung-Yu Wu,
Ming-Kai Tsai:
VHF Bandpass Filter Design Using CMOS Transresistance Amplifiers.
ISCAS 1993: 990-993 |
| 1990 |
|---|
| 2 | EE | Chung-Yu Wu,
Ming-Chuen Shiau:
Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(9): 1002-1009 (1990) |
| 1985 |
|---|
| 1 | EE | Chung-Yu Wu,
Jen-Sheng Hwang,
Chih Chang,
Ching-Chu Chang:
An Efficient Timing Model for CMOS Combinational Logic Gates.
IEEE Trans. on CAD of Integrated Circuits and Systems 4(4): 636-650 (1985) |
