| 2008 |
|---|
| 22 | EE | Chad M. Lawler,
Michael A. Harper,
Stephen A. Szygenda,
Mitchell A. Thornton:
Components of disaster-tolerant computing: analysis of disaster recovery, IT application downtime and executive visibility.
IJBIS 3(3): 317-331 (2008) |
| 2004 |
|---|
| 21 | | Ralph Marczynski,
Mitchell A. Thornton,
Stephen A. Szygenda:
Test vector generation and classification using FSM traversals.
ISCAS (5) 2004: 309-312 |
| 20 | EE | Lun Li,
Mitchell A. Thornton,
Stephen A. Szygenda:
A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking.
ISVLSI 2004: 32-38 |
| 1997 |
|---|
| 19 | EE | Youngmin Hur,
Saghir A. Shaikh,
Silvian Goldenberg,
D. Kacprzak,
Stephen A. Szygenda:
Concurrent Fault and Design Error Simulation in Interactive Simulation Automation System.
Annual Simulation Symposium 1997: 168-176 |
| 18 | EE | Saghir A. Shaikh,
Stephen A. Szygenda:
Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation.
Annual Simulation Symposium 1997: 64- |
| 17 | | Charles Wiley,
A. T. Campbell III,
Stephen A. Szygenda,
Donald S. Fussell,
Fred Hudson:
Multiresolution BSP Trees Applied to Terrain, Transparency, and General Objects.
Graphics Interface 1997: 88-96 |
| 1996 |
|---|
| 16 | EE | Youngmin Hur,
Stephen A. Szygenda:
A Simulation Tool for Design Error Models Utilizing Error Compression and Sampling.
Annual Simulation Symposium 1996: 212-220 |
| 15 | | Saghir A. Shaikh,
Silvian Goldenberg,
Stephen A. Szygenda:
CON2FERS: A Concurrent Concurrent Fault and Design Error Simulator.
PDPTA 1996: 109-112 |
| 1995 |
|---|
| 14 | EE | Youngmin Hur,
Stephen A. Szygenda:
Special purpose array processor for digital logic simulation.
Annual Simulation Symposium 1995: 297-302 |
| 13 | | Youngmin Hur,
Stephen A. Szygenda,
E. Scott Fehr,
Granville E. Ott,
Sungho Kang:
Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation.
HPCA 1995: 340-347 |
| 12 | EE | Brian Grayson,
Saghir A. Shaikh,
Stephen A. Szygenda:
Statistics on concurrent fault and design error simulation.
ICCD 1995: 622-627 |
| 1994 |
|---|
| 11 | EE | Sungho Kang,
Stephen A. Szygenda:
Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling.
IEEE Design & Test of Computers 11(1): 18-26 (1994) |
| 10 | EE | Sungho Kang,
Stephen A. Szygenda:
The simulation automation system (SAS); concepts, implementation, and results.
IEEE Trans. VLSI Syst. 2(1): 89-99 (1994) |
| 1993 |
|---|
| 9 | | Sungho Kang,
Stephen A. Szygenda:
Automatic VHDL Model Generation System.
CHDL 1993: 353-360 |
| 8 | | Charles Wiley,
K. M. Lau,
Stephen A. Szygenda:
m3D: A Multidimensional Dynamic Configurable Router.
ISCAS 1993: 1857-1860 |
| 1992 |
|---|
| 7 | EE | Cheng-I Chuang,
Stephen A. Szygenda,
James D. Baker:
The automatic element routine generator: an automatic programming tool for functional simulator design.
Annual Simulation Symposium 1992: 84-90 |
| 6 | | Sungho Kang,
Stephen A. Szygenda:
Modeling and Simulation of Design Errors.
ICCD 1992: 443-446 |
| 1990 |
|---|
| 5 | EE | Jin-Hyeung Kong,
Stephen A. Szygenda:
MixMOS: a mixed-level simulator for digital MOS circuits using a new algebraic approach.
Computer-Aided Design 22(10): 618-632 (1990) |
| 1988 |
|---|
| 4 | EE | Asad Karim,
Stephen A. Szygenda:
SMARTGEN: The Implementation of an Expert System for the Generation of Digital Logic Diagnostic Tests.
IEA/AIE (Vol. 1) 1988: 355-360 |
| 1976 |
|---|
| 3 | | N. Billawala,
Stephen A. Szygenda,
Ewald W. Thomson:
A Data Structure and Drive Mechanism for a Table-Driven Simulation System Employing Multilevel Structural Representations of Digital Systems.
ICSE 1976: 151-157 |
| 2 | | Stephen A. Szygenda,
Edward W. Thomson:
Modeling and Digital Simulation for Design Verification and Diagnosis.
IEEE Trans. Computers 25(12): 1242-1253 (1976) |
| 1973 |
|---|
| 1 | | John M. Hemphill,
Stephen A. Szygenda:
Deriving Design Guidelines for Diagnosable Computer Systems.
ISCA 1973: 131-135 |
