| 2008 |
|---|
| 80 | EE | Yuki Watanabe,
Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Arithmetic module generator with algorithm optimization capability.
ISCAS 2008: 1796-1799 |
| 79 | EE | Yuki Watanabe,
Naofumi Homma,
Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.
ISMVL 2008: 112-117 |
| 78 | EE | Naofumi Homma,
T. Aoki,
Tatsuo Higuchi:
A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams.
IEEE Trans. Computers 57(12): 1633-1646 (2008) |
| 77 | EE | Koichi Ito,
Takafumi Aoki,
Hiroshi Nakajima,
Koji Kobayashi,
Tatsuo Higuchi:
A Palmprint Recognition Algorithm Using Phase-Only Correlation.
IEICE Transactions 91-A(4): 1023-1030 (2008) |
| 2007 |
|---|
| 76 | EE | Yuki Watanabe,
Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Application of symbolic computer algebra to arithmetic circuit verification.
ICCD 2007: 25-32 |
| 75 | EE | Naofumi Homma,
Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams.
ISMVL 2007: 31 |
| 2006 |
|---|
| 74 | EE | Koichi Ito,
Ayumi Morita,
Takafumi Aoki,
Hiroshi Nakajima,
Koji Kobayashi,
Tatsuo Higuchi:
A Fingerprint Recognition Algorithm Combining Phase-Based Image Matching and Feature-Based Matching.
ICB 2006: 316-325 |
| 73 | EE | Hiroshi Nakajima,
Koji Kobayashi,
Makoto Morikawa,
Atsushi Katsumata,
Koichi Ito,
Takafumi Aoki,
Tatsuo Higuchi:
Fast and Robust Fingerprint Identification Algorithm and Its Application to Residential Access Controller.
ICB 2006: 326-333 |
| 72 | EE | Koichi Ito,
Takafumi Aoki,
Hiroshi Nakajima,
Koji Kobayashi,
Tatsuo Higuchi:
A Palmprint Recognition Algorithm using Phase-Based Image Matching.
ICIP 2006: 2669-2672 |
| 71 | EE | Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi,
Hiroshi Inokawa,
Katsuhiko Nishiguchi,
Yasuo Takahashi:
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors.
ISMVL 2006: 19 |
| 70 | EE | Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic.
ISMVL 2006: 2 |
| 69 | EE | Naofumi Homma,
Yuki Watanabe,
Takafumi Aoki,
Tatsuo Higuchi:
Formal Design of Arithmetic Circuits Based on Arithmetic Description Language.
IEICE Transactions 89-A(12): 3500-3509 (2006) |
| 68 | EE | Koichi Ito,
Masahiko Hiratsuka,
Takafumi Aoki,
Tatsuo Higuchi:
A Shortest Path Search Algorithm Using an Excitable Digital Reaction-Diffusion System.
IEICE Transactions 89-A(3): 735-743 (2006) |
| 67 | EE | Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic.
IEICE Transactions 89-C(11): 1645-1654 (2006) |
| 2005 |
|---|
| 66 | EE | Koichi Ito,
Ayumi Morita,
Takafumi Aoki,
Tatsuo Higuchi,
Hiroshi Nakajima,
Koji Kobayashi:
A fingerprint recognition algorithm using phase-based image matching for low-quality fingerprints.
ICIP (2) 2005: 33-36 |
| 65 | EE | Katsuhiko Degawa,
Takafumi Aoki,
Hiroshi Inokawa,
Tatsuo Higuchi,
Yasuo Takahashi:
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors.
ISMVL 2005: 32-38 |
| 2004 |
|---|
| 64 | EE | Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Multiplier Block Synthesis Using Evolutionary Graph Generation.
Evolvable Hardware 2004: 79-82 |
| 63 | | Naofumi Homma,
Jun Sakiyama,
Taihei Wakamatsu,
Takafumi Aoki,
Tatsuo Higuchi:
A systematic approach for analyzing fast addition algorithms using counter tree diagrams.
ISCAS (5) 2004: 197-200 |
| 62 | EE | Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi,
Hiroshi Inokawa,
Yasuo Takahashi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic.
ISMVL 2004: 262-268 |
| 61 | EE | Hiroshi Inokawa,
Yasuo Takahashi,
Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions.
ISMVL 2004: 269-274 |
| 60 | EE | Kazuya Ishida,
Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH.
ISMVL 2004: 334-339 |
| 59 | EE | Yoshiko Yasuda,
Shinichi Kawamoto,
Atsushi Ebata,
Jun Okitsu,
Tatsuo Higuchi:
An On-line Backup Function for a Clustered NAS System (X-NAS).
MSST 2004: 165-169 |
| 58 | EE | Masanori Natsui,
Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation.
PPSN 2004: 342-351 |
| 2003 |
|---|
| 57 | EE | Naofumi Homma,
Masanori Natsui,
Takafumi Aoki,
Tatsuo Higuchi:
VLSI circuit design using an object-oriented framework of evolutionary graph generation system.
IEEE Congress on Evolutionary Computation (1) 2003: 115-122 |
| 56 | EE | Yoshiko Yasuda,
Shinichi Kawamoto,
Atsushi Ebata,
Jun Okitsu,
Tatsuo Higuchi:
Concept and Evaluation of X-NAS: A Highly Scalable NAS System.
IEEE Symposium on Mass Storage Systems 2003: 219- |
| 55 | EE | Koichi Ito,
Takafumi Aoki,
Tatsuo Higuchi:
Design of a digital reaction-diffusion system for restoring blurred fingerprint images.
ISCAS (4) 2003: 77-80 |
| 54 | EE | Naofumi Homma,
Takafumi Aoki,
Makoto Motegi,
Tatsuo Higuchi:
A framework of evolutionary graph generation system and its application to circuit synthesis.
ISCAS (5) 2003: 201-204 |
| 53 | EE | Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic.
ISMVL 2003: 213-220 |
| 52 | EE | Jun Sakiyama,
Takafumi Aoki,
Tatsuo Higuchi:
Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms.
ISMVL 2003: 91-98 |
| 51 | EE | Takafumi Aoki,
Naofumi Homma,
Tatsuo Higuchi:
Evolutionary Synthesis of Arithmetic Circuit Structures.
Artif. Intell. Rev. 20(3-4): 199-232 (2003) |
| 2002 |
|---|
| 50 | EE | Mochamad Hariadi,
Akio Harada,
Takafumi Aoki,
Tatsuo Higuchi:
Pixel-wise human motion segmentation using learning vector quantization.
ICARCV 2002: 1439-1444 |
| 49 | EE | Yasushi Yuminaka,
Tatsuya Morishita,
Takafumi Aoki,
Tatsuo Higuchi:
Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI.
ISMVL 2002: 54-60 |
| 48 | EE | Masanori Natsui,
Takafumi Aoki,
Tatsuo Higuchi:
Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis.
ISMVL 2002: 96- |
| 47 | EE | Makoto Motegi,
Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis.
PPSN 2002: 831-840 |
| 46 | | Dingjun Chen,
Takafumi Aoki,
Naofumi Homma,
Toshiki Terasaki,
Tatsuo Higuchi:
Graph-based evolutionary design of arithmetic circuits.
IEEE Trans. Evolutionary Computation 6(1): 86-100 (2002) |
| 2001 |
|---|
| 45 | EE | Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Evolutionary graph generation system with transmigration capability for arithmetic circuit design.
ISCAS (5) 2001: 171-174 |
| 44 | | Masahiko Hiratsuka,
Takafumi Aoki,
Tatsuo Higuchi:
A Model of Reaction-Diffusion Cellular Automata for Massively Parallel Molecular Computing.
ISMVL 2001: 247-252 |
| 43 | | Masanori Natsui,
Takafumi Aoki,
Tatsuo Higuchi:
Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation.
ISMVL 2001: 253-258 |
| 2000 |
|---|
| 42 | EE | Takafumi Aoki,
Kimihiko Nakazawa,
Tatsuo Higuchi:
High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables.
ISMVL 2000: 345- |
| 41 | EE | Yasushi Yuminaka,
Osamu Katoh,
Yoshisat Sasaki,
Takafumi Aoki,
Tatsuo Higuchi:
An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access.
ISMVL 2000: 430-437 |
| 1999 |
|---|
| 40 | EE | Takafumi Aoki,
Ken-ichi Hoshi,
Tatsuo Higuchi:
Redundant Complex Arithmetic and Its Application to Complex Multiplier Design.
ISMVL 1999: 200-207 |
| 1998 |
|---|
| 39 | EE | Takafumi Aoki,
Tatsuo Higuchi:
Set-Valued Logic Circuits for Next Generation VLSI Architectures.
ISMVL 1998: 140-147 |
| 38 | EE | Yasushi Yuminaka,
Yoshisat Sasaki,
Takafumi Aoki,
Tatsuo Higuchi:
Wave-Parallel Computing Systems using Multiple-Valued Pseudo-Orthogonal Sequences.
ISMVL 1998: 148- |
| 1997 |
|---|
| 37 | EE | Takafumi Aoki,
Hiroaki Amada,
Tatsuo Higuchi:
Real/Complex Reconfigurable Arithmetic Using Redundant Complex Number Systems.
IEEE Symposium on Computer Arithmetic 1997: 200-207 |
| 36 | EE | Masahiko Hiratsuka,
Takafumi Aoki,
Tatsuo Higuchi:
Enzyme Transistor Circuits for Biomolecular Computing.
ISMVL 1997: 47- |
| 1996 |
|---|
| 35 | EE | Yasushi Yuminaka,
Yoshisato Sasaki,
Takafumi Aoki,
Tatsuo Higuchi:
Wave-Parallel Computing Technique for Neural Networks Based on Amplitude-Modulated Waves.
ISMVL 1996: 210-215 |
| 34 | | Shoji Kawahito,
Makoto Ishida,
Tasuro Nakamura,
Michitaka Kameyama,
Tatsuo Higuchi:
Author's Reply.
IEEE Trans. Computers 45(5): 639 (1996) |
| 33 | EE | Qiangfu Zhao,
Tatsuo Higuchi:
Efficient learning of NN-MLP based on individual evolutionary algorithm.
Neurocomputing 13(2-4): 201-215 (1996) |
| 32 | EE | Qiangfu Zhao,
Tatsuo Higuchi:
Minimization of nearest neighbor classifiers based on individual evolutionary algorithm.
Pattern Recognition Letters 17(2): 125-131 (1996) |
| 1995 |
|---|
| 31 | | Shinichi Shionoya,
Takafumi Aoki,
Tatsuo Higuchi:
Multiwave Interconnection Networks for MCM-based Parallel Processing.
Euro-Par 1995: 593-607 |
| 30 | EE | Young-Ho Lee,
Masayuki Kawamata,
Tatsuo Higuchi:
Design of 2-D state-space digital filters with powers-of-two coefficients based on a genetic algorithm.
ICIP 1995: 2133-2136 |
| 29 | EE | Y. Ohi,
Takafumi Aoki,
Tatsuo Higuchi:
Redundant Complex Number Systems.
ISMVL 1995: 14-19 |
| 28 | EE | S. Sakurai,
Takafumi Aoki,
Tatsuo Higuchi:
Wire-Free Computing Circuits Using Optical Wave-Casting.
ISMVL 1995: 8-13 |
| 27 | | Qiangfu Zhao,
Tatsuo Higuchi:
Individual Evolutionary Algorithm and its Application to Learning of Nearest Neighbor Based MLP.
IWANN 1995: 396-403 |
| 1994 |
|---|
| 26 | | Masayuki Kawamata,
Jun Imakubo,
Tatsuo Higuchi:
Optimal Design Method of 2-D IIR Digital Filters Based on a Simple Genetic Algorithm.
ICIP (1) 1994: 780-784 |
| 25 | | Masayuki Kawamata,
Masaki Nagahisa,
Tatsuo Higuchi:
Multi-resolution Tree Search for Iterated Transformation Theory-Based Coding.
ICIP (3) 1994: 137-141 |
| 24 | | Yasushi Yuminaka,
Takafumi Aoki,
Tatsuo Higuchi:
Design of Wave-Parallel Computing Circuits for Densely Connected Architectures.
ISMVL 1994: 207-214 |
| 23 | | Takashi Takimoto,
Takafumi Aoki,
Tatsuo Higuchi:
Design of Multiplex Interconnection Networks for Massively Parallel Computing Systems.
ISMVL 1994: 231-238 |
| 22 | | Shoji Kawahito,
Makoto Ishida,
Tetsuro Nakamura,
Michitaka Kameyama,
Tatsuo Higuchi:
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.
IEEE Trans. Computers 43(1): 34-42 (1994) |
| 1993 |
|---|
| 21 | | Yasushi Iwata,
Masayuki Kawamata,
Tatsuo Higuchi:
Design of Fine Grain VLSI Array Processor for Real-time 2-D Digital Filtering.
ISCAS 1993: 1559-1562 |
| 20 | | Masayuki Kawamata,
Eiichiro Kawakami,
Tatsuo Higuchi:
Realization of lattice-form separable-denominator 2D adaptive filters.
ISCAS 1993: 295-298 |
| 19 | | Satoshi Aragaki,
Takahiro Hanyu,
Tatsuo Higuchi:
A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions.
ISMVL 1993: 170-175 |
| 18 | | Takafumi Aoki,
Tatsuo Higuchi:
Impact of Interconnection-Free Biomolecular Computing.
ISMVL 1993: 271-276 |
| 17 | | Yasushi Yuminaka,
Takafumi Aoki,
Tatsuo Higuchi:
Design of Set-Valued Logic Networks for Wave-Parallel Computing.
ISMVL 1993: 277-282 |
| 1992 |
|---|
| 16 | | Takahiro Hanyu,
Kouichi Takeda,
Tatsuo Higuchi:
Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems.
ISMVL 1992: 274-281 |
| 15 | | Shuichi Maeda,
Takafumi Aoki,
Tatsuo Higuchi:
Set-Valued Logic Networks Based on Optical Wavelength Multiplexing.
ISMVL 1992: 282-290 |
| 14 | | Katsuhiko Shimabukuro,
Michitaka Kameyama,
Tatsuo Higuchi:
Design of a Multiple-Valued VLSI Processor for Digital Control.
ISMVL 1992: 322-329 |
| 13 | | Makoto Honda,
Michitaka Kameyama,
Tatsuo Higuchi:
Residue Arithmetic Based Multiple-Valued VLSI Image Processor.
ISMVL 1992: 330-336 |
| 12 | | Saneaki Tamaki,
Michitaka Kameyama,
Tatsuo Higuchi:
Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits.
ISMVL 1992: 382-388 |
| 11 | | Takafumi Aoki,
Michitaka Kameyama,
Tatsuo Higuchi:
Interconnection-Free Biomolecular Computing.
IEEE Computer 25(11): 41-50 (1992) |
| 1991 |
|---|
| 10 | | Somchai Kittichaikoonkit,
Michitaka Kameyama,
Tatsuo Higuchi:
High-Performance VLSI Processor for Robot Inverse Dynamics Computation.
ICCD 1991: 608-611 |
| 9 | | Takahiro Hanyu,
Yasushi Kojima,
Tatsuo Higuchi:
A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems.
ISMVL 1991: 16-23 |
| 8 | | Takafumi Aoki,
Michitaka Kameyama,
Tatsuo Higuchi:
Design of Interconnection-Free Biomolecular Computing System.
ISMVL 1991: 173-180 |
| 7 | | Takahiro Hanyu,
Tatsuo Higuchi:
A Floating-Gate-MOS-Based Multiple-Valued Associative Memory.
ISMVL 1991: 24-31 |
| 6 | | Yasushi Yuminaka,
Takafumi Aoki,
Tatsuo Higuchi:
Design of a Set Logic Network Based on Frequency Multiplexing and Its Applications to Image Processing.
ISMVL 1991: 8-15 |
| 1990 |
|---|
| 5 | | Takahiro Hanyu,
Tatsuo Higuchi:
Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices.
ISMVL 1990: 18-23 |
| 4 | | Michitaka Kameyama,
Masahiro Nomura,
Tatsuo Higuchi:
Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System.
ISMVL 1990: 355-362 |
| 1988 |
|---|
| 3 | | Michitaka Kameyama,
Shoji Kawahito,
Tatsuo Higuchi:
A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits.
IEEE Computer 21(4): 43-56 (1988) |
| 1977 |
|---|
| 2 | | Tatsuo Higuchi,
Michitaka Kameyama:
Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters.
IEEE Trans. Computers 26(12): 1212-1221 (1977) |
| 1 | | Michitaka Kameyama,
Tatsuo Higuchi:
Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module.
IEEE Trans. Computers 26(12): 1297-1302 (1977) |
