| 2008 |
|---|
| 16 | EE | Chia-Nan Yeh,
Yen-Tai Lai:
A novel flash analog-to-digital converter.
ISCAS 2008: 2250-2253 |
| 2006 |
|---|
| 15 | EE | Chia-Nan Yeh,
Yen-Tai Lai:
Low power readout control circuit for high resolution CMOS image sensor.
ISCAS 2006 |
| 2005 |
|---|
| 14 | EE | Yen-Tai Lai,
Hsin-Ya Lai,
Chia-Nan Yeh:
Placement for the reconfigurable datapath architecture.
ISCAS (2) 2005: 1875-1878 |
| 13 | EE | Yen-Tai Lai,
Yung-Chuan Jiang,
Hong-Ming Chu:
BDD decomposition for mixed CMOS/PTL logic circuit synthesis.
ISCAS (6) 2005: 5649-5652 |
| 12 | EE | Chi-Chou Kao,
Yen-Tai Lai:
An efficient algorithm for finding the minimal-area FPGA technology mapping.
ACM Trans. Design Autom. Electr. Syst. 10(1): 168-186 (2005) |
| 2004 |
|---|
| 11 | EE | Chi-Chou Kao,
Yen-Tai Lai:
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction.
ASP-DAC 2004: 719-724 |
| 2001 |
|---|
| 10 | EE | Lih-Yang Wang,
Yen-Tai Lai:
Graph-theory-based simplex algorithm for VLSI layout spacingproblems with multiple variable constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(8): 967-979 (2001) |
| 1999 |
|---|
| 9 | EE | Chi-Chou Kao,
Yen-Tai Lai:
A routability and performance driven technology mapping algorithm for LUT based FPGA designs.
ISCAS (1) 1999: 474-477 |
| 8 | EE | Yen-Tai Lai,
Chi-Chou Kao,
Wu-Chien Shieh:
A quadratic programming method for interconnection crosstalk minimization.
ISCAS (6) 1999: 270-273 |
| 1997 |
|---|
| 7 | EE | Yen-Tai Lai,
Ping-Tsung Wang:
Hierarchical interconnection structures for field programmable gate arrays.
IEEE Trans. VLSI Syst. 5(2): 186-196 (1997) |
| 1995 |
|---|
| 6 | EE | Lih-Yang Wang,
Yen-Tai Lai,
Bin-Da Liu,
Tin-Chung Chang:
Performance-directed compaction for VLSI symbolic layouts.
Computer-Aided Design 27(1): 65-74 (1995) |
| 1994 |
|---|
| 5 | | Ping-Tsung Wang,
Kun-Nen Chen,
Yen-Tai Lai:
A High Performance FPGA with Hierarchical Interconnection Structure.
ISCAS 1994: 239-242 |
| 1993 |
|---|
| 4 | EE | Lih-Yang Wang,
Yen-Tai Lai,
Bin-Da Liu,
Ting-Chung Chang:
A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths.
ICCAD 1993: 703-708 |
| 3 | | Lih-Yang Wang,
Yen-Tai Lai,
Bin-Da Liu,
Tin-Chung Chang:
Layout Compaction with Minimzed Delay Bound on Timing Critical Paths.
ISCAS 1993: 1849-1852 |
| 1990 |
|---|
| 2 | | Yen-Tai Lai,
Sany M. Leinwand:
A Theory of Rectangular Dual Graphs.
Algorithmica 5(4): 467-483 (1990) |
| 1988 |
|---|
| 1 | EE | Yen-Tai Lai,
Sany M. Leinwand:
Algorithms for floorplan design via rectangular dualization.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(12): 1278-1289 (1988) |
