| 2007 |
|---|
| 12 | EE | Harry I. A. Chen,
Edward K. W. Loo,
James B. Kuo,
Marek Syrzycki:
Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS.
PATMOS 2007: 453-462 |
| 2005 |
|---|
| 11 | EE | James B. Kuo:
Evolution of Bootstrap Techniques in Low-Voltage CMOS Digital VLSI Circuits for SoC Applications, invited.
IWSOC 2005: 143-148 |
| 2003 |
|---|
| 10 | EE | P. C. Chen,
James B. Kuo:
Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI.
ISCAS (5) 2003: 441-444 |
| 1996 |
|---|
| 9 | EE | Y. G. Chen,
James B. Kuo:
A unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 µm NMOS devices.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(2): 256-258 (1996) |
| 1994 |
|---|
| 8 | | James B. Kuo,
K. W. Su,
J. H. Lou:
A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit.
ISCAS 1994: 323-326 |
| 7 | | James B. Kuo,
B. Y. Chen,
Mark W. Mao:
A Radical-Partitioned Neural Network System Using a Modified Sigmoid Function and a Wight-Dotted Radical Selector for Large-Volume Chinese Characters Recognition VLSI.
ISCAS 1994: 331-334 |
| 1993 |
|---|
| 6 | | Mark W. Mao,
B. Y. Chen,
James B. Kuo:
A Coded Block Neural Network System Suitable for VLSI Implementation Using an Adaptive Learning-rate Epoch-based Back Propagation Technique.
ISCAS 1993: 1967-1970 |
| 5 | | James B. Kuo,
H. P. Chen,
H. J. Huang:
A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI.
ISCAS 1993: 2027-2030 |
| 1992 |
|---|
| 4 | EE | H.-C. Chow,
W.-S. Feng,
James B. Kuo:
An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(12): 1522-1528 (1992) |
| 3 | EE | Mark W. Mao,
James B. Kuo:
A coded block adaptive neural network system with a radical-partitioned structure for large-volume Chinese characters recognition.
Neural Networks 5(5): 835-841 (1992) |
| 1989 |
|---|
| 2 | EE | James B. Kuo,
Tsen-Shau Yang,
Robert W. Dutton,
Bruce A. Wooley:
Two-dimensional transient analysis of a collector-up ECL inverter.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(10): 1038-1045 (1989) |
| 1 | EE | James B. Kuo,
G. P. Rosseel,
Robert W. Dutton:
Two-dimensional analysis of a merged BiPMOS device.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(8): 929-932 (1989) |
