2007 |
25 | EE | Ulrich Ramacher:
Challenges and prospects of SDR for mobile phones.
ICCD 2007: 215 |
24 | EE | Ulrich Ramacher:
Software-Defined Radio Prospects for Multistandard Mobile Phones.
IEEE Computer 40(10): 62-69 (2007) |
23 | EE | Ahmed Amine Jerraya,
Olivier Franza,
Markus Levy,
Masao Nakaya,
Pierre G. Paulin,
Ulrich Ramacher,
Deepu Talla,
Wayne Wolf:
Roundtable: Envisioning the Future for Multiprocessor SoC.
IEEE Design & Test of Computers 24(2): 174-183 (2007) |
2005 |
22 | EE | Francine Bacchini,
Jan M. Rabaey,
Allan Cox,
Frank Lane,
Rudy Lauwereins,
Ulrich Ramacher,
David Witt:
Wireless platforms: GOPS for cents and MilliWatts.
DAC 2005: 351-352 |
21 | EE | Werner Hemmert,
Marcus Holmberg,
Ulrich Ramacher:
Temporal Sound Processing by Cochlear Nucleus Octopus Neurons.
ICANN (1) 2005: 583-588 |
20 | EE | Peter Benkart,
Alexander Kaiser,
Andreas Munding,
Markus Bschorr,
Hans-Jörg Pfleiderer,
Erhard Kohn,
Arne Heittmann,
Holger Huebner,
Ulrich Ramacher:
3D Chip Stack Technology Using Through-Chip Interconnects.
IEEE Design & Test of Computers 22(6): 512-518 (2005) |
19 | EE | Joachim M. Buhmann,
Tilman Lange,
Ulrich Ramacher:
Image Segmentation by Networks of Spiking Neurons.
Neural Computation 17(5): 1010-1031 (2005) |
2004 |
18 | | Jörg Schreiter,
Ulrich Ramacher,
Arne Heittmann,
Daniel Matolin,
René Schüffny:
Pulse coupled neural networks with adaptive synapses for image segmentation.
ARCS Workshops 2004: 275-282 |
17 | EE | Wolfgang Raab,
Hans-Martin Blüthgen,
Ulrich Ramacher:
A low-power memory hierarchy for a fully programmable baseband processor.
WMPI 2004: 102-106 |
2003 |
16 | EE | Wolfgang Raab,
Nico Brüls,
J. A. Ulrich Hachmann,
Jens Harnisch,
Ulrich Ramacher,
Christian Sauer,
Axel Techmer:
A 100-GOPS Programmable Processor for Vehicle Vision Systems.
IEEE Design & Test of Computers 20(1): 8-16 (2003) |
15 | EE | Ulrich Ramacher,
Nico Brüls,
J. A. Ulrich Hachmann,
Jens Harnisch,
Wolfgang Raab,
Axel Techmer:
100 GOPS vision processor for automotive applications.
SIGARCH Computer Architecture News 31(1): 60-68 (2003) |
2002 |
14 | EE | Arne Heittmann,
Ulrich Ramacher,
Daniel Matolin,
Jörg Schreiter,
René Schüffny:
An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights.
ICANN 2002: 1293-1298 |
13 | EE | Ulrich Ramacher:
Application Specific Embedded Processors for Next Generation Communication Systems.
ICCD 2002 |
2001 |
12 | EE | Chr. Werner,
R. Göttsche,
A. Wörner,
Ulrich Ramacher:
Crosstalk noise in future digital CMOS circuits.
DATE 2001: 331-335 |
1999 |
11 | | Ulrich Ramacher,
Wolfgang Raab,
Wolfgang Kabatzke:
Prototyp eines Bildrechners für Echtzeitbildverarbeitung in Industrie- und Medientechnik.
PEARL 1999: 102-110 |
1996 |
10 | | Ulrich Ramacher:
SEE-1 - A Vision System for Use in Real World Environments.
ICANN 1996: 17 |
1995 |
9 | EE | Ulrich Ramacher,
Wolfgang Raab,
J. A. Ulrich Hachmann,
Jörg Beichter,
Nico Brüls,
Matthias Wesseling,
Elisabeth Sicheneder,
Joachim Gläß,
Andreas Wurz,
Reinhard Männer:
SYNAPSE-1: a high-speed general purpose parallel neurocomputer system.
IPPS 1995: 774-781 |
1993 |
8 | | Ulrich Ramacher,
Jörg Beichter,
Nico Brüls,
Elisabeth Sicheneder:
Architecture and VLSI Design of a VLSI Neural Signal Processor.
ISCAS 1993: 1975-1978 |
7 | EE | Ulrich Ramacher,
Peter Schildberg:
Recent Developments In Neurodynamics And Their Impact On The Design Of Neuro-Chips.
Int. J. Neural Syst. 4(4): 309-316 (1993) |
6 | EE | Ulrich Ramacher,
Wolfgang Raab,
Joachim K. Anlauf,
J. A. Ulrich Hachmann,
Jörg Beichter,
Nico Brüls,
Matthias Wesseling,
Elisabeth Sicheneder,
Reinhard Männer,
Joachim Gläß,
Andreas Wurz:
Multiprocessor And Memory Architecture Of The Neurocomputer Synapse-1.
Int. J. Neural Syst. 4(4): 333-336 (1993) |
5 | EE | Ulrich Ramacher:
Hamiltonian dynamics of neural networks.
Neural Networks 6(4): 547-557 (1993) |
4 | | Jörg Beichter,
Nico Brüls,
Elisabeth Sicheneder,
Ulrich Ramacher,
Heinrich Klar:
Design of a general-purpose neural signal processor.
Neurocomputing 5(1): 17-23 (1993) |
3 | EE | Ulrich Ramacher,
Jörg Beichter,
Nico Brüls:
A general-purpose signal processor architecture for neurocomputing and preprocessing applications.
VLSI Signal Processing 6(1): 45-56 (1993) |
1992 |
2 | | Ulrich Ramacher:
SYNAPSE - A Neurocomputer that Synthesizes Neural Algorithms on a Parallel Systolic Engine.
J. Parallel Distrib. Comput. 14(3): 306-318 (1992) |
1989 |
1 | | Matthias Wesseling,
Ulrich Ramacher,
Karl Goser:
Evaluation and Comparison of Selected WSI Reconfiguration Architectures in Terms of Yield and Yield per Area.
Fehlertolerierende Rechensysteme 1989: 74-84 |