2003 |
16 | EE | Kumaraswamy Ponnambalam,
Abbas Seifi,
Jiri Vlach:
Yield optimization with correlated design parameters and non-symmetrical marginal distributions.
ISCAS (4) 2003: 736-739 |
1999 |
15 | EE | Abbas Seifi,
Kumaraswamy Ponnambalam,
Jiri Vlach:
Probabilistic design of integrated circuits with correlated input parameters.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(8): 1214-1219 (1999) |
1997 |
14 | | C.-J. Richard Shi,
Anthony Vannelli,
Jiri Vlach:
Performance-Driven Layer Assignment by Integer Linear Programming and Path-Constrained Hypergraph Partitioning.
J. Heuristics 3(3): 225-243 (1997) |
1995 |
13 | | Juraj Valsa,
Jiri Vlach:
SWANN - A Program for Analysis of Switched Analog Nonlinear Networks.
ISCAS 1995: 1752-1755 |
1994 |
12 | | Jacek Wojciechowski,
Jiri Vlach:
Spectra of Graphs with Circulant Blocks and their Applications.
ISCAS 1994: 161-164 |
11 | | Francisco V. Fernández,
Georges G. E. Gielen,
Lawrence Huelsman,
Agnieszka Konczykowska,
Stefano Manetti,
Willy M. C. Sansen,
Jiri Vlach:
Pleasures, Perils and Pitfalls of Symbolic Analysis.
ISCAS 1994: 451-457 |
1993 |
10 | | Jiri Vlach,
Ajoy Opal,
Jacek Wojciechowski:
Simulation of Networks with Inconsistent Initial Conditions.
ISCAS 1993: 1627-1630 |
9 | EE | Jacek Wojciechowski,
Jiri Vlach:
Ellipsoidal method for design centering and yield estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1570-1579 (1993) |
1991 |
8 | | David Bedrosian,
Jiri Vlach:
An Accelerated Steady-State Method for Networks with Internally Controlled Switches.
ICCAD 1991: 24-27 |
7 | EE | Genhong Ruan,
Jiri Vlach,
James A. Barby,
Ajoy Opal:
Analog functional simulator for multilevel systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 565-576 (1991) |
6 | EE | Jiri Vlach,
James A. Barby,
Anthony Vannelli,
T. Talkhan,
C.-J. Richard Shi:
Group delay as an estimate of delay in logic.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(7): 949-953 (1991) |
1990 |
5 | EE | Genhong Ruan,
Jiri Vlach,
James A. Barby:
Logic simulation with current-limited switches.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(2): 133-141 (1990) |
1988 |
4 | EE | James A. Barby,
Jiri Vlach,
Kishore Singhal:
Polynomial splines for MOSFET model approximation.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(5): 557-566 (1988) |
3 | EE | Ernst Christen,
Jiri Vlach:
NETOPT-a program for multiobjective design of linear networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(5): 567-577 (1988) |
2 | EE | Genhong Ruan,
Jiri Vlach,
James A. Barby:
Current-limited switch-level timing simulator for MOS logic networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(6): 659-667 (1988) |
1987 |
1 | EE | Rakesh Chadha,
Kishore Singhal,
Jiri Vlach,
Ernst Christen,
Milan Vlach:
WATOPT -- An Optimizer for Circuit Applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(3): 472-479 (1987) |