| |
| 1999 | ||
|---|---|---|
| 6 | EE | L. Yihong, T. K. Ho, A. B. Rad, Stephen P. S. Lam: A Sigma GIi/D/1/infinity queue with heterogeneous input/output slot times. Computer Communications 22(12): 1136-1149 (1999) |
| 5 | EE | Y. H. Long, T. K. Ho, A. B. Rad, Stephen P. S. Lam: A study of the generalised max-min fair rate allocation for ABR control in ATM. Computer Communications 22(13): 1247-1259 (1999) |
| 1994 | ||
| 4 | Stephen P. S. Lam: A 21/2-Dimensional Systolic Array Architecture. ISCAS 1994: 243-246 | |
| 3 | Stephen P. S. Lam: An Iterative Array Processor Architecture for Matrix Computation. PARLE 1994: 777-780 | |
| 1993 | ||
| 2 | Stephen P. S. Lam: A New Approach to Reconfigure Faulty Systolic Array. ISCAS 1993: 1929-1932 | |
| 1992 | ||
| 1 | Stephen P. S. Lam: A Novel Sorting Array Processor. CONPAR 1992: 193-204 | |
| 1 | T. K. Ho | [5] [6] |
| 2 | Y. H. Long | [5] |
| 3 | A. B. Rad | [5] [6] |
| 4 | L. Yihong | [6] |