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Chetana Nagendra

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1996
6EEChetana Nagendra, Robert Michael Owens, Mary Jane Irwin: Design tradeoffs in high speed multipliers and FIR filters. VLSI Design 1996: 29-32
5EEManjit Borah, Chetana Nagendra, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin: An optimal time multiplication free algorithm for edge detection on a mesh. VLSI Signal Processing 13(1): 67-75 (1996)
1995
4EEChetana Nagendra, Robert Michael Owens, Mary Jane Irwin: Unifying carry-sum and signed-digital number representations for low power. ISLPD 1995: 15-20
3EEChetana Nagendra, Robert Michael Owens, Mary Jane Irwin: Digit pipelined arithmetic on fine-grain array processors. VLSI Signal Processing 9(3): 193-209 (1995)
1994
2 Manjit Borah, Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin: The MGAP: A High Performance, User Programmable, Multifunctional Architecture for DS. HICSS (1) 1994: 96-104
1EEChetana Nagendra, Robert Michael Owens, Mary Jane Irwin: Power-delay characteristics of CMOS adders. IEEE Trans. VLSI Syst. 2(3): 377-381 (1994)

Coauthor Index

1Manjit Borah [2] [5]
2Mary Jane Irwin [1] [2] [3] [4] [5] [6]
3Robert Michael Owens [1] [2] [3] [4] [5] [6]
4Mohan Vishwanath [5]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)