1996 | ||
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1 | EE | S. Bhattacharjee, J. Bhattacharya, U. Raghavendra, Debashis Saha, Parimal Pal Chaudhuri: A VLSI architecture for cellular automata based parallel data compression. VLSI Design 1996: 270-275 |
1 | S. Bhattacharjee | [1] |
2 | J. Bhattacharya | [1] |
3 | Parimal Pal Chaudhuri | [1] |
4 | Debashis Saha | [1] |