| |
| 2005 | ||
|---|---|---|
| 7 | EE | P. V. Ananda Mohan: Floating Capacitance Simulation Using Current Conveyors. Journal of Circuits, Systems, and Computers 14(1): 123-128 (2005) |
| 2003 | ||
| 6 | EE | P. V. Ananda Mohan: Fast implementations of Montgomery's modular multiplication algorithm. ISCAS (4) 2003: 125-128 |
| 1999 | ||
| 5 | EE | P. V. Ananda Mohan: Efficient Design of Binary to RNS Converters. Journal of Circuits, Systems, and Computers 9(3-4): 145-154 (1999) |
| 1996 | ||
| 4 | EE | D. V. Poornaiah, P. V. Ananda Mohan: A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. VLSI Design 1996: 69-72 |
| 1995 | ||
| 3 | EE | D. V. Poornaiah, P. V. Ananda Mohan: Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. VLSI Design 1995: 392-397 |
| 1994 | ||
| 2 | P. V. Ananda Mohan: Novel Design for Binary to RNS Converters. ISCAS 1994: 357-360 | |
| 1993 | ||
| 1 | Y. V. Ramana Rao, P. V. Ananda Mohan: Novel oversampled A/D converters based on error spectrum shaping. ISCAS 1993: 212-215 | |
| 1 | D. V. Poornaiah | [3] [4] |
| 2 | Y. V. Ramana Rao | [1] |