P. V. Ananda Mohan

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7EEP. V. Ananda Mohan: Floating Capacitance Simulation Using Current Conveyors. Journal of Circuits, Systems, and Computers 14(1): 123-128 (2005)
6EEP. V. Ananda Mohan: Fast implementations of Montgomery's modular multiplication algorithm. ISCAS (4) 2003: 125-128
5EEP. V. Ananda Mohan: Efficient Design of Binary to RNS Converters. Journal of Circuits, Systems, and Computers 9(3-4): 145-154 (1999)
4EED. V. Poornaiah, P. V. Ananda Mohan: A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. VLSI Design 1996: 69-72
3EED. V. Poornaiah, P. V. Ananda Mohan: Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. VLSI Design 1995: 392-397
2 P. V. Ananda Mohan: Novel Design for Binary to RNS Converters. ISCAS 1994: 357-360
1 Y. V. Ramana Rao, P. V. Ananda Mohan: Novel oversampled A/D converters based on error spectrum shaping. ISCAS 1993: 212-215

Coauthor Index

1D. V. Poornaiah [3] [4]
2Y. V. Ramana Rao [1]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)