S. Potla

1996
2	EE	R. P. Suresh, P. Venugopal, S. Tamizh Selvam, S. Potla: Combined Effect of Grain Boundary Depletion and PolySi/Oxide Interface Depletion on Drain Characteristics of a p-MOSFET. VLSI Design 1996: 156-161
1995
1	EE	Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh: A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology. VLSI Design 1995: 192-

Coauthor Index

1	Varna Puvvada	[1]
2	S. Tamizh Selvam	[1] [2]
3	P. R. Suresh	[1]
4	R. P. Suresh	[2]
5	P. Venugopal	[2]