D. V. Poornaiah

1996
2	EE	D. V. Poornaiah, P. V. Ananda Mohan: A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. VLSI Design 1996: 69-72
1995
1	EE	D. V. Poornaiah, P. V. Ananda Mohan: Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. VLSI Design 1995: 392-397

Coauthor Index

1

P. V. Ananda Mohan

[1] [2]