1996 | ||
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2 | EE | D. V. Poornaiah, P. V. Ananda Mohan: A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. VLSI Design 1996: 69-72 |
1995 | ||
1 | EE | D. V. Poornaiah, P. V. Ananda Mohan: Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. VLSI Design 1995: 392-397 |
1 | P. V. Ananda Mohan | [1] [2] |