| |
| 1996 | ||
|---|---|---|
| 3 | EE | Krzysztof Bilinski, Erik L. Dagless, Jonathan M. Saul: Behavioral Synthesis of Complex Parallel Controllers. VLSI Design 1996: 186-191 |
| 1995 | ||
| 2 | EE | Aigo Lu, Erik L. Dagless, Jonathan M. Saul: DART: delay and routability driven technology mapping for LUT based FPGAs. ICCD 1995: 409-414 |
| 1994 | ||
| 1 | EE | Krzysztof Bilinski, Erik L. Dagless, Jonathan M. Saul, Marian Adamski: Parallel controller synthesis from a Petri net specification. EURO-DAC 1994: 96-101 |
| 1 | Marian Adamski | [1] |
| 2 | Krzysztof Bilinski | [1] [3] |
| 3 | Erik L. Dagless | [1] [2] [3] |
| 4 | Aigo Lu | [2] |