| 2006 |
|---|
| 5 | EE | A. R. Nayak,
John R. Barry,
G. Feyh,
Steven W. McLaughlin:
Timing Recovery With Frequency Offset and Random Walk: Cramer-Rao Bound and a Phase-Locked Loop Postprocessor.
IEEE Transactions on Communications 54(10): 1896-1896 (2006) |
| 4 | EE | A. R. Nayak,
John R. Barry,
G. Feyh,
Steven W. McLaughlin:
Timing Recovery With Frequency Offset and Random Walk: Cramér-Rao Bound and a Phase- Locked Loop Postprocessor.
IEEE Transactions on Communications 54(11): 2004-2013 (2006) |
| 1996 |
|---|
| 3 | EE | Sunil R. Das,
N. Goel,
Wen-Ben Jone,
A. R. Nayak:
Syndrome signature in output compaction for VLSI BIST.
VLSI Design 1996: 337-338 |
| 1995 |
|---|
| 2 | EE | Sunil R. Das,
H. T. Ho,
Wen-Ben Jone,
A. R. Nayak:
An improved output compaction technique for built-in self-test in VLSI circuits.
VLSI Design 1995: 403-407 |
| 1994 |
|---|
| 1 | | A. R. Nayak,
Wen-Ben Jone,
Sunil R. Das:
Designing General-Purpose Fault-Tolerant Distributed Systems - A Layered Approach.
ICPADS 1994: 360-365 |
