ISQED 2000:
San Jose,
California,
USA
1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA.
IEEE Computer Society 2000, ISBN 0-7695-0525-2 BibTeX
@proceedings{DBLP:conf/isqed/2000,
title = {1st International Symposium on Quality of Electronic Design (ISQED
2000), 20-22 March 2000, San Jose, CA, USA},
booktitle = {ISQED},
publisher = {IEEE Computer Society},
year = {2000},
isbn = {0-7695-0525-2},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Evening Panel Discussion
Plenary Session
Panel Discussion
DSM Modeling
Emerging Process and Device Technology
- Jiann S. Yuan:
Overview of SiGe Technology Modeling and Application.
67-72
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- Lifeng Wu, Jingkun Fang, Heting Yan, Ping Chen, Alvin I-Hsien Chen, Yoshifumi Okamoto, Chune-Sin Yeh, Zhihong Liu, Nobufusa Iwanishi, Norio Koike, Hirokazu Yonezawa, Yoshiyuki Kawakami:
GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design.
73-80
Electronic Edition (link) BibTeX
- Ji-Soong Park, Chul-Hong Park, Sang-Uhk Rhie, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong, Hyung-Woo Kim, Sun-Il Yoo:
An Efficient Rule-Based OPC Approach Using a DRC Tool for 0.18mum ASIC.
81-86
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- Kwan-Do Kim, Young-Kwan Park, Jun-Ha Lee, Jeong-Taek Kong, Hee-Sung Kang, Young-Wug Kim, Seok-Jin Kim:
Three Dimensional Analysis of Thermal Degradation Effects in FDSOI MOSFET's.
87-
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Quality of Design and EDA Tools
Emerging Integrity Issues
- Kenji Shimazaki, Hiroyuki Tsujikawa, Seijiro Kojima, Shouzou Hirano:
LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator.
129-136
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- Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng:
Dynamic Timing Analysis Considering Power Supply Noise Effects.
137-144
Electronic Edition (link) BibTeX
- Zhiping Yu, Dan Yergeau, Robert W. Dutton, O. Sam Nakagawa, Norman Chang, Shen Lin, Weize Xie:
Full Chip Thermal Simulation.
145-150
Electronic Edition (link) BibTeX
- Wonjae L. Kang, Brad Potts, Ray Hokinson, John Riley, David Doman, Frank Cano, N. S. Nagaraj, Noel Durrant:
Enabling DIR(Designing-In-Reliability) through CAD Capabilities.
151-156
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- Mariagrazia Graziano, Marco Delaurenti, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Noise Safety Design Methodologies.
157-
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Low Power Test
Evening Panel Discussion
Plenary Session
Quality of IP Blocks
Impact of Emerging Processes on Design Quality
Poster Session
- Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj:
Power Bus Maximum Voltage Drop in Digital VLSI Circuits.
263-268
Electronic Edition (link) BibTeX
- Mely Chen Chi, Shih-Hsu Huang:
A Reliable Clock Tree Design Methodology for ASIC Designs.
269-274
Electronic Edition (link) BibTeX
- Peter H. Chen, Sunil Malkani, Chun-Mou Peng, James Lin:
Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion.
275-282
Electronic Edition (link) BibTeX
- Donald J. Dent:
Project Management for System-on-Chip Using Multi-Chip Modules.
283-290
Electronic Edition (link) BibTeX
- Mohamed Dessouky, Marie-Minerve Louërat:
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits.
291-298
Electronic Edition (link) BibTeX
- Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou:
On Testability of Multiple Precharged Domino Logic.
299-304
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- Makoto Ikeda, Hideyuki Aoki, Kunihiro Asada:
DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path.
305-308
Electronic Edition (link) BibTeX
- J. L. Knighten, N. W. Smith, L. O. Hoeft, J. T. DiBene II:
EMI Common-Mode Current Dependence on Delay Skew Imbalance in High Speed Differential Transmission Lines Operating at 1 Gigabit/second Data Rates.
309-314
Electronic Edition (link) BibTeX
- Wieslaw Kuzmicz:
Internet-Based Virtual Manufacturing: A Verification Tool for IC Designs.
315-320
Electronic Edition (link) BibTeX
- Rong Lin:
A Reconfigurable Low-Power High-Performance Matrix Multiplier Design.
321-328
Electronic Edition (link) BibTeX
- Mehdi M. Mechaik:
Electrical Characterization of Signal Routability and Performance.
329-336
Electronic Edition (link) BibTeX
- Steffen Rochel, N. S. Nagaraj:
Full-Chip Signal Interconnect Analysis for Electromigration Reliability.
337-340
Electronic Edition (link) BibTeX
- Erik A. McShane, Krishna Shenai:
Correct-by-Design CAD Enhancement for EMI Signal Integrity.
341-346
Electronic Edition (link) BibTeX
- Alvernon Walker, Parag K. Lala:
A Transition Based BIST Approach for Passive Analog Circuits.
347-354
Electronic Edition (link) BibTeX
- Jin Ding, David Moloney, Xiaojun Wang:
Aliasing-Free Space and Time Compactions with Limited Overhead.
355-360
Electronic Edition (link) BibTeX
- Matthew Worsman, Mike W. T. Wong, Y. S. Lee:
A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis Quality.
361-368
Electronic Edition (link) BibTeX
- Gin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen:
An Automated Shielding Algorithm and Tool For Dynamic Circuits.
369-374
Electronic Edition (link) BibTeX
- Li-Fu Chang, Keh-Jeng Chang, Christophe J. Bianchi:
A Proposal for Accurately Modeling Frequency-Dependent On-Chip Interconnect Impedance.
375-378
Electronic Edition (link) BibTeX
- Jean-Pierre Gukguen, Pierre Bricaud:
Applying the OpenMORE Assessment Program for IP Cores.
379-
Electronic Edition (link) BibTeX
Panel Discussion
Quality Definitions and Metrics
Low Power Design and Test
Panel Discussion
Design for Manufacturability
- Sani R. Nassif:
Design for Variability in DSM Technologies.
451-454
Electronic Edition (link) BibTeX
- Alessandra Nardi, Andrea Neviani, Carlo Guardiani:
Realistic Worst-Case Modeling by Performance Level Principal Component Analysis.
455-460
Electronic Edition (link) BibTeX
- Valery Axelrad, Nicolas B. Cobb, M. O'Brien, Thuy Do, Tom Donnelly, Yuri Granik, Emile Y. Sahouria, Victor Boksha, Artur Balasinski:
Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Designs.
461-466
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- Gary W. Maier, Shawn Smith:
Electronic Process Limited Yield.
467-474
Electronic Edition (link) BibTeX
- Mehdi M. Mechaik:
Effects of Package Stackups on Microprocessor Performance.
475-
Electronic Edition (link) BibTeX
VDSM Capacitive and Inductive Issues
- Kathirgamar Aingaran, Fabian Klass, Chin-Man Kim, Chaim Amir, Joydeep Mitra, Eileen You, Jamil Mohd, Sai-keung Dong:
Coupling Noise Analysis for VLIS and ULSI Circuits.
485-490
Electronic Edition (link) BibTeX
- Tong Xiao, Malgorzata Marek-Sadowska:
Efficient Delay Calculation in Presence of Crosstalk.
491-498
Electronic Edition (link) BibTeX
- Bruno Franzini, Cristiano Forzan, Davide Pandini, Primo Scandolara, Alessandro Dal Fabbro:
Crosstalk Aware Static Timing Analysis: A Two Step Approach.
499-504
Electronic Edition (link) BibTeX
- Peivand F. Tehrani, Shang Woo Chyou, Uma Ekambaram:
Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk.
505-512
Electronic Edition (link) BibTeX
- Shen Lin, Norman Chang, O. Sam Nakagawa:
Quick On-Chip Self- and Mutual-Inductance Screen.
513-
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:26:17 2009
by Michael Ley (ley@uni-trier.de)
