13. PATMOS 2003:
Torino,
Italy
Jorge Juan-Chico, Enrico Macii (Eds.):
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings.
Lecture Notes in Computer Science 2799 Springer 2003, ISBN 3-540-20074-6 BibTeX
@proceedings{DBLP:conf/patmos/2003,
editor = {Jorge Juan-Chico and
Enrico Macii},
title = {Integrated Circuit and System Design, Power and Timing Modeling,
Optimization and Simulation, 13th International Workshop, PATMOS
2003, Torino, Italy, September 10-12, 2003, Proceedings},
booktitle = {PATMOS},
publisher = {Springer},
series = {Lecture Notes in Computer Science},
volume = {2799},
year = {2003},
isbn = {3-540-20074-6},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynote Speech
Gate-Level Modeling and Design
Low Level Modeling and Characterization
- Tim Schoenauer, Jörg Berthold, Christoph Heer:
Reduced Leverage of Dual Supply voltages in Ultra Deep Submicron Technologies.
41-50
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- José Luis Rosselló, Jaume Segura:
A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates.
51-59
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- Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
CMOS Gate Sizing under Delay Constraint.
60-69
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- E. Seebacher, Gerhard Rappitsch, H. Höller:
Process Characterization for Low VTH and Low Power Design.
70-79
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- Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodriguez-Sánchez:
Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results.
80-89
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Interconnect Modeling and Optimization
- Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni:
Effects of Temperature in Deep-Submicron Global Interconnect Optimization.
90-100
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- Jérôme Lescot, François J. R. Clément:
Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits.
101-110
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- Sampo Tuuna, Jouni Isoaho:
Estimation of Crosstalk Noise for On-Chip Buses.
111-120
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- M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization.
121-130
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- Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel:
Interconnect Driven Low Power High-Level Synthesis.
131-140
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Asynchronous Techniques
- Joep L. W. Kessels, Ad M. G. Peeters, Suk-Jin Kim:
Bridging Clock Domains by Synchronizing the Mice in the Mousetrap.
141-150
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- Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida:
Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization.
151-160
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- Milos Krstic, Eckhard Grass:
New GALS Technique for Datapath Architectures.
161-170
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- João Leonardo Fragoso, Gilles Sicard, Marc Renaudin:
Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders.
171-180
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- Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin:
Statistic Implementation of QDI Asynchronous Primitives.
181-191
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Keynote Speech
Industrial Session
RTL Power Modeling and Memory Optimisation
- B. Arts, N. van der Eng, Marc J. M. Heijligers, H. Munk, Frans Theeuwen, Luca Benini, Enrico Macii, A. Milia, Roberto Maro, A. Bellu:
Statistical Power Estimation of Behavioral Descriptions.
197-207
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- Maurizio Bruno, Alberto Macii, Massimo Poncino:
A Statistic Power Model for Non-synthetic RTL Operators.
208-218
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- Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose:
Energy Efficient Register Renaming.
219-228
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- S. Cservany, Jean-Marc Masgonty, Christian Piguet:
Stand-by Power Reduction for Storage Circuits.
229-238
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- José L. Ayala, Marisa Luisa López-Vallejo:
A Unified Framework for Power-Aware Design of Embedded Systems.
239-248
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High-Level Modeling
- Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria:
A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems.
249-258
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- Fei Li, Lei He, Joseph M. Basile, Rakesh Patel, Hema Ramamurthy:
High Level Area and Current Estimation.
259-268
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- Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner:
Switching Activity Estimation in Non-linear Architectures.
269-278
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- Spiridon Nikolaidis, Nikolaos Kavvadias, T. Laopoulos, Labros Bisdounis, Spyros Blionas:
Instruction Level Energy Modeling for Pipelined Processors.
279-288
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- Marc Leeman, David Atienza, Francky Catthoor, Vincenzo De Florio, Geert Deconinck, Jose Manuel Mendias, Rudy Lauwereins:
Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level.
289-298
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Power Efficient Technologies and Designs
- Vineela Manne, Akhilesh Tyagi:
An Adiabatic Charge Pump Based Charge Recycling Design Style.
299-308
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- Jürgen Fischer, Ettore Amirante, Francesco Randazzo, Giuseppe Iannaccone, Doris Schmitt-Landsiedel:
Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing.
309-318
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- Tae-Chan Kim, Meejoung Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim:
Low Power Response Time Accelerator with Full Resolution for LCD Panel.
319-327
Electronic Edition (link) BibTeX
- V. Ferentinos, M. Milia, Gauthier Lafruit, Jan Bormans, Francky Catthoor:
Memory Compaction and Power Optimization for Wavelet-Based Coders.
328-337
Electronic Edition (link) BibTeX
- Emil Hjalmarson, Robert Hägglund, Lars Wanhammar:
Design Space Exploration and Trade-Offs in Analog Amplifier Design.
338-347
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Keynote Speech
Communication Modeling and Design
Low Power Issues in Processors and Multimedia
- Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija:
Energy Optimization of High-Performance Circuits.
399-408
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- Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor:
Instruction Buffering Exploration for Low Energy Embedded Processors.
409-419
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- Amirali Baniasadi:
Power-Aware Branch Predictor Update for High-Performance Processors.
420-429
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- Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas:
Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms.
430-439
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- Massimo Ravasi, Marco Mattavelli, Paul R. Schumacher, Robert D. Turney:
High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder.
440-450
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Poster Session
- Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne:
Metric Definition for Circuit Speed Optimization.
451-460
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- Grzegorz Tosik, Frédéric Gaffiot, Zbigniew Lisik, Ian O'Connor, Faress Tissafi-Drissi:
Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies.
461-470
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- Bahman Javadi, Mohsen Naderi, Hossein Pedram, Ali Afzali-Kusha, Mohammad K. Akbari:
An Asynchronous Viterbi Decoder for Low-Power Applications.
471-480
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- Eugeni Isern, Miquel Roca, Francesc Moll:
Analysis of the Contribution of Interconnect Effects in the Energy Dissipation of VLSI Circuits.
481-490
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- Raúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta:
A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application.
491-500
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- David Guerrero, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán:
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits.
501-510
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- Dongsheng Wang, Peter Suaris, Nan-Chi Chou:
A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages.
511-519
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- Byung-Soo Choi, Dong-Ik Lee:
Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus.
520-529
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- Akihito Sakanaka, Toshinori Sato:
Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction.
530-539
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- Andrea Acquaviva, Alessandro Bogliolo:
A Bottom-Up Approach to On-Chip Signal Integrity.
540-549
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- Wen-Tsong Shiue, Weetit Wanalertlak:
Advanced Cell Modeling Techniques Based on Polynomial Expressions.
550-558
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- Paul Flugger:
RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches.
559-568
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- Anatoly Prihozhy, Marco Mattavelli, Daniel Mlynek:
Data Dependences Critical Path Evaluation at C/C++ System Level Description.
569-579
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- Javier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién:
A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements.
580-589
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- Chee Lee, Wen-Tsong Shiue:
Consideration of Control System and Memory Contributions in Practical Resource-Constrained Scheduling for Low Power.
590-598
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- Tae-Chan Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim:
Low Power Cache with Successive Tag Comparison Algorithm.
599-606
Electronic Edition (link) BibTeX
- Konstantinos Tatas, K. Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis:
FPGA Architecture Design and Toolset for Logic Implementation.
607-616
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- María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida:
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis.
617-627
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Copyright © Sat May 16 23:32:37 2009
by Michael Ley (ley@uni-trier.de)
