SBCCI 2004: Pernambuco, Brazil

Edna Natividade da Silva Barros, Flávio Rech Wagner, Luigi Carro, Franz-Josef Rammig (Eds.): Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004. ACM 2004 BibTeX

Tutorials

Enrico Macii:
RTL power estimation and optimization. 1
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Chandu Visweswariah:
Statistical analysis and design: from picoseconds to probabilities. 2
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Mike Hutton:
Architecture and CAD for FPGAs. 3
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José Luis Huertas:
Test and design-for-test of mixed-signal integrated circuits. 4
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Raul Camposano:
Will the ASIC survive? 5
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Armando Carbonari:
Avionic systems overview. 6
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Enrico Macii:
Leakage power optimization in standard-cell designs. 7
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Mike Hutton:
Advances and trends in FPGA design. 8
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César Augusto Dueñas M.:
Verification and test challenges in SoC designs. 9
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Partial reconfigurable architectures

Ewerson Carvalho, Ney Calazans, Eduardo Wenzel Brião, Fernando Moraes:
PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems. 10-15
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Paulo Sérgio B. do Nascimento, Paulo Romero Martins Maciel, Manoel Eusebio de Lima, Remy Eskinazi Sant'Anna, Abel Guilhermino S. Filho:
A partial reconfigurable architecture for controllers based on Petri nets. 16-21
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Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich:
Task scheduling for heterogeneous reconfigurable computers. 22-27
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Michael Hübner, Tobias Becker, Jürgen Becker:
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration. 28-32
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Analog design

Hamilton Klimach, Alfredo Arnaud, Márcio C. Schneider, Carlos Galup-Montoro:
Characterization of MOS transistor current mismatch. 33-38
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Antonio Petraglia, Jorge M. Cañive, Mariane R. Petraglia:
A 0.8 mum CMOS switched-capacitor video filter. 39-43
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Andre Vilas Boas, J. B. D. Soldera, Alfredo Olmos:
A 1.8V supply multi-frequency digitally trimmable on-chip IC oscillator with low-voltage detection capability. 44-48
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Eric E. Fabris, Luigi Carro, Sergio Bampi:
Modeling and designing high performance analog reconfigurable circuits. 49-54
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Verification (co-organized with LA-TTTC)

Fernando Cortez Sica, Claudionor José Nunes Coelho Jr., José Augusto Miranda Nacif, Harry Foster, Antônio Otávio Fernandes:
Exception handling in microprocessors using assertion libraries. 55-59
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Ghiath Al Sammane, Julien Schmaltz, Diana Toma, Pierre Ostier, Dominique Borrione:
TheoSim: combining symbolic simulation and theorem proving for hardware verification. 60-65
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Karina R. G. da Silva, Elmar U. K. Melcher, Guido Araujo, Valdiney Alves Pimenta:
An automatic testbench generation tool for a SystemC functional verification methodology. 66-70
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Fulvio Corno, Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante:
A multi-level approach to the dependability analysis of networked systems based on the CAN protocol. 71-75
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RF design

José Vieira do Vale Neto:
Design sequence for a LC-tank voltage controlled oscillator in CMOS for RF. 76-81
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Virgínia Helena Varotto Baroncini, Oscar da Costa Gouveia-Filho:
Design of RF CMOS low noise amplifiers using a current based MOSFET model. 82-87
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C. P. Moreira, Eric Kerherve, P. Jarry, A. A. Shirakawa, Didier Belot:
Dual-mode RF receiver front-end using a 0.25-µm 60-GHz f_TSiGe: C BiCMOS7RF technology. 88-93
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Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije:
A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology. 94-99
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Test (co-organized with LA-TTTC)

Carlos Eduardo Savioli, Claudio C. Czendrodi, José Vicente Calvano, Antonio Carneiro de Mesquita Filho:
ATPG for fault diagnosis on analog electrical networks using evolutionary techniques. 100-104
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Antonio Andrade Jr., Érika F. Cota, Marcelo Lubaszewski:
Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST. 105-110
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Alexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes:
Reducing test time with processor reuse in network-on-chip based systems. 111-116
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Physical modeling and analysis

Tudor Murgan, Clemens Schlachta, Mihail Petrov, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis:
Accurate capture of timing parameters in inductively-coupled on-chip interconnects. 117-122
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João M. S. Silva, L. Miguel Silveira:
Issues in parallelizing multigrid-based substrate model extraction and analysis. 123-128
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Gabriella Trucco, Giorgio Boselli, Valentino Liberali:
An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs. 129-134
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Applications of reconfigurable architectures

Klaus Danne:
Distributed arithmetic FPGA design with online scalable size and performance. 135-140
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Alexander Thomas, Thomas Zander, Jürgen Becker:
Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures. 141-146
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Low-power analog design

Edgar Mauricio Camacho-Galeano, Carlos Galup-Montoro, Márcio C. Schneider:
An ultra-low-power self-biased current reference. 147-150
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Alfredo Arnaud, Carlos Galup-Montoro:
A fully integrated physical activity sensing circuit for implantable pacemakers. 151-156
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Embedded systems

Antonio Carlos Schneider Beck, Luigi Carro:
A VLIW low power Java processor for embedded applications. 157-162
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Raimundo S. Barreto, Marília Neves, Meuse N. Oliveira Jr., Paulo Romero Martins Maciel, Eduardo Tavares, Ricardo Massa Ferreira Lima:
A formal software synthesis approach for embedded hard real-time systems. 163-168
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Leandro Buss Becker, Marco A. Wehrmeister, Carlos Eduardo Pereira:
Power and performance tuning in the synthesis of real-time scheduling algorithms for embedded applications. 169-174
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Márcio Oyamada, Felipe Zschornack, Flávio Rech Wagner:
Accurate software performance estimation using domain classification and neural networks. 175-180
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Dedicated circuits

Mário C. B. Osorio, Carlos A. Sampaio, André Inácio Reis, Renato P. Ribas:
Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic. 181-185
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Michel Leong, Pedro Vasconcelos, Jorge R. Fernandes, Leonel Sousa:
A programmable cellular neural network circuit. 186-191
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Timo Vogt, Norbert Wehn, Philippe Alves:
A multi-standard channel-decoder for base-station applications. 192-197
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Michael J. Thul, Norbert Wehn:
FPGA implementation of parallel turbo-decoders. 198-203
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Networks-on-chip

Cesar Albenes Zeferino, Frederico G. M. E. Santo, Altamiro Amadeu Susin:
ParIS: a parameterizable interconnect switch for networks-on-chip. 204-209
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Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner:
A switch architecture and signal synchronization for GALS system-on-chips. 210-215
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Rodrigo Soares, Ivan Saraiva Silva, Arnaldo Azevedo:
When reconfigurable architecture meets network-on-chip. 216-221
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Mixed analog-digital design

Marcel Jacomet, Josef Goette, Venanz Zbinden, Christian Narvaez:
On the dynamic behavior of a novel digital-only sigma--delta A/D converter. 222-227
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David Camarero, Jean-François Naviner, Patrick Loumeau:
Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters. 228-232
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Hans-Dieter Wohlmuth, Daniel Kehrer:
A low power 13-Gb/s 2^7-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS. 233-236
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Design methods

Vagner S. Rosa, Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi:
An improved synthesis method for low power hardwired FIR filters. 237-241
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Christian Meise, Christoph Grimm:
A SystemC based case study of a sensor application using the BeCom modeling methodology for virtual prototyping. 242-247
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Mauricio Ayala-Rincón, Ricardo P. Jacobi, Luis G. A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein:
Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic. 248-253
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Logic and physical CAD

Vinícius Correia, André Reis:
Advanced technology mapping for standard-cell generators. 254-259
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Mircea R. Stan, Fatih Hamzaoglu, David Garrett:
Non-Manhattan maze routing. 260-265
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Low-power gate design

Luiz Alberto P. Melek, Márcio C. Schneider, Carlos Galup-Montoro:
Body-bias compensation technique for SubThreshold CMOS static logic gates. 267-272
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Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh:
Low-power dual V_th pseudo dual V_dd domino circuits. 273-277
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Frank Sill, Frank Grassert, Dirk Timmermann:
Low power gate-level design with mixed-V_th (MVT) techniques. 278-282
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