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Andrea Calimera

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2009
7EEAndrea Calimera, Enrico Macii, Massimo Poncino: NBTI-aware sleep transistor design for reliable power-gating. ACM Great Lakes Symposium on VLSI 2009: 333-338
2008
6EEAndrea Calimera, Enrico Macii, Massimo Poncino, R. Iris Bahar: Temperature-insensitive synthesis using multi-vt libraries. ACM Great Lakes Symposium on VLSI 2008: 5-10
5EEAndrea Calimera, Luca Benini, Enrico Macii: Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints. DATE 2008: 973-978
4EEAshoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. ISCAS 2008: 2761-2764
3EEAndrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino: Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. ISLPED 2008: 217-220
2007
2EEAndrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. ACM Great Lakes Symposium on VLSI 2007: 501-504
1EEAshoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. DATE 2007: 1544-1549

Coauthor Index

1R. Iris Bahar [3] [6]
2Luca Benini [1] [2] [4] [5]
3Alberto Macii [1] [2] [4]
4Enrico Macii [1] [2] [3] [4] [5] [6] [7]
5Massimo Poncino [1] [2] [3] [4] [6] [7]
6Antonio Pullini [2] [4]
7Ashoka Visweswara Sathanur [1] [2] [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)