10. PATMOS 2000:
Göttingen,
Germany
Dimitrios Soudris, Peter Pirsch, Erich Barke (Eds.):
Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings.
Lecture Notes in Computer Science 1918 Springer 2000, ISBN 3-540-41068-6 BibTeX
@proceedings{DBLP:conf/patmos/2000,
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, PATMOS 2000, G{\"o}ttingen,
Germany, September 13-15, 2000, Proceedings},
booktitle = {PATMOS},
publisher = {Springer},
series = {Lecture Notes in Computer Science},
volume = {1918},
year = {2000},
isbn = {3-540-41068-6},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Opening
RTL Power Modeling
- Manuela Anton, Mauro Chinosi, Daniele Sirtori, Roberto Zafalon:
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques.
3-13
Electronic Edition (link) BibTeX
- Alessandro Bogliolo, Enrico Macii, Virgil Mihailovici, Massimo Poncino:
Power Models for Semi-autonomous RTL Macros.
14-23
Electronic Edition (link) BibTeX
- Gerd Jochens, Lars Kruse, Eike Schmidt, Ansgar Stammermann, Wolfgang Nebel:
Power Macro-Modelling for Firm-Macro.
24-35
Electronic Edition (link) BibTeX
- Crina Anton, Pierluigi Civera, Ionel Colonescu, Enrico Macii, Massimo Poncino, Alessandro Bogliolo:
RTL Estimation of Steering Logic Power.
36-46
Electronic Edition (link) BibTeX
Power Estimation and Optimization
- Nikolaos D. Zervas, S. Theoharis, Athanasios Kakarountas, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis:
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers.
47-55
Electronic Edition (link) BibTeX
- Achim Freimann:
Framework for High-Level Power Estimation of Signal Processing Architectures.
56-65
Electronic Edition (link) BibTeX
- Claudia Kretzschmar, Robert Siegmund, Dietmar Müller:
Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses.
66-75
Electronic Edition (link) BibTeX
- George Theodoridis, S. Theoharis, Nikolaos D. Zervas, Constantinos E. Goutis:
Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions.
76-87
Electronic Edition (link) BibTeX
System-Level Design
Transistor-Level Modeling
Asynchronous Circuit Design
Power Efficient Technologies
Design of Multimedia Processing Applications
- Santanu Dutta:
Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip.
225-232
Electronic Edition (link) BibTeX
- Kristof Denolf, Peter Vos, Jan Bormans, Ivo Bolsens:
Cost-Efficient C-Level Design of an MPEG-4 Video Decoder.
233-242
Electronic Edition (link) BibTeX
- Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis:
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications.
243-254
Electronic Edition (link) BibTeX
Adiabatic Design and Arithmetic Modules
Analog-Digital Circuits Modeling
- Raúl Jiménez, Antonio J. Acosta, Eduardo J. Peralías, Adoración Rueda:
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits.
295-305
Electronic Edition (link) BibTeX
- Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel:
PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits.
306-315
Electronic Edition (link) BibTeX
- Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia:
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits.
316-326
Electronic Edition (link) BibTeX
- Tom Wichmann, Manfred Thole:
Computer Aided Generation of Analytic Models for Nonlinear Function Blocks.
327-335
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:32:37 2009
by Michael Ley (ley@uni-trier.de)
