18. PATMOS 2008:
Lisbon,
Portugal
Lars Svensson, José Monteiro (Eds.):
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers.
Lecture Notes in Computer Science 5349 Springer 2009, ISBN 978-3-540-95947-2 BibTeX
Low-Leakage and Subthreshold Circuits
Low-Power Methods and Models
- Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.
42-51
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- Roni Wiener, Gila Kamhi, Moshe Y. Vardi:
Intelligate: Scalable Dynamic Invariant Learning for Power Reduction.
52-61
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- Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura:
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption.
62-71
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- Yoni Aizik, Gila Kamhi, Yael Zbar, Hadas Ronen, Muhammad Abozaed:
Power-Aware Design via Micro-architectural Link to Implementation.
72-81
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- Vasily G. Moshnyaga:
Untraditional Approach to Computer Energy Reduction.
82-92
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Arithmetic and Memories
- Ioannis Kouretas, Vassilis Paliouras:
Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication.
93-102
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- Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Lars Lundheim, Asghar Havashki:
Power Optimization of Parallel Multipliers in Systems with Variable Word-Length.
103-115
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- Florian Bauer, Georg Georgakos, Doris Schmitt-Landsiedel:
A Design Space Comparison of 6T and 8T SRAM Core-Cells.
116-125
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- Yan Li, Helmut Schneider, Florian Schnabel, Roland Thewes, Doris Schmitt-Landsiedel:
Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization.
126-135
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Variability and Statistical Timing
- Massimo Alioto, Gaetano Palumbo, Melita Pennisi:
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic.
136-145
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- Monica Figueiredo, Rui L. Aguiar:
A Study on CMOS Time Uncertainty with Technology Scaling.
146-155
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- Bing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann:
Static Timing Model Extraction for Combinational Circuits.
156-166
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- Walter Schneider, Manuel Schmidt, Bing Li, Ulf Schlichtmann:
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA.
167-177
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- Howard Chen, Scott Neely, Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah:
Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power.
178-187
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Synchronization and Interconnect
Power Supplies and Switching Noise
- Thomas Ordas, Mathieu Lisart, Etienne Sicard, Philippe Maurine, Lionel Torres:
Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits.
229-236
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- Giorgio Boselli, Valentina Ciriani, Valentino Liberali, Gabriella Trucco:
A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint.
237-246
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- Pedro Marques Morgado, Paulo F. Flores, José C. Monteiro, Luis Miguel Silveira:
Generating Worst-Case Stimuli for Accurate Power Grid Analysis.
247-257
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- Nuno Dias, Marcelino Santos, Floriberto Lima, Beatriz Borges, Júlio Paisana:
Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization.
258-267
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Low-Power Circuits; Reconfigurable Architectures
- Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija:
Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements.
268-276
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- Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo:
A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation.
277-286
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- Maurice Keller, William P. Marnane:
Energy Efficient Elliptic Curve Processor.
287-296
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- Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala:
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing.
297-306
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- Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich:
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.
307-317
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Poster Session 1:
Circuits and Methods
- Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers.
318-327
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- Omid Mirmotahari, Yngvar Berg:
Ultra Low Voltage High Speed Differential CMOS Inverter.
328-337
Electronic Edition (link) BibTeX
- Marco Bucci, Raimondo Luzzi, Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti:
Differential Capacitance Analysis.
338-347
Electronic Edition (link) BibTeX
- Martin Simlastík, Viera Stopjaková:
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey.
348-358
Electronic Edition (link) BibTeX
- Antoine Courtay, Johann Laurent, Olivier Sentieys, Nathalie Julien:
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses.
359-368
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Poster Session 2:
Power and Delay Modeling
- Ruzica Jevtic, Carlos Carreras:
Analytical High-Level Power Model for LUT-Based Components.
369-378
Electronic Edition (link) BibTeX
- Gustavo Rau de Almeida Callou, Paulo Romero Martins Maciel, Ermeson Carneiro de Andrade, Bruno Costa e Silva Nogueira, Eduardo Tavares, Meuse N. Oliveira Jr.:
A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption.
379-388
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- Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero, Paulino Ruiz-de-Clavijo, Julian Viejo:
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates.
389-398
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- Felipe Machado, Teresa Riesgo, Yago Torroja:
Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level.
399-408
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- Francesc Moll, Joan Figueras, Antonio Rubio:
Data Dependence of Delay Distribution for a Planar Bus.
409-418
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Power Optimizations Addressing Reconfigurable Architectures
- Juanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner, Jürgen Becker:
Towards Novel Approaches in Design Automation for FPGA Power Optimization.
419-428
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- Tim Todman, Haohuan Fu, Brittle Tsoi, Oskar Mencer, Wayne Luk:
Smart Enumeration: A Systematic Approach to Exhaustive Search.
429-438
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- Kostas Siozios, Dimitrios Soudris:
An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs.
439-448
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- Mladen Berekovic, Frank Bouwens, Tom Vander Aa, Diederik Verkest:
Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor.
449-457
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Keynotes (Abstracts)
Copyright © Sat May 16 23:32:39 2009
by Michael Ley (ley@uni-trier.de)
