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1997 | ||
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3 | EE | Dariusz Badura, Andrzej Hlawiczka: Low Cost Bist for Edac Circuits. Asian Test Symposium 1997: 410-415 |
1989 | ||
2 | Dariusz Badura: Efficiency of Self-Test Path as a Test Pattern Generator and Test Response Compactor. Fehlertolerierende Rechensysteme 1989: 368-378 | |
1987 | ||
1 | Andrzej Hlawiczka, Dariusz Badura: Universal Test Controller Chip for Board Self Test. Fehlertolerierende Rechensysteme 1987: 165-175 |
1 | Andrzej Hlawiczka | [1] [3] |