ICCD 2007:
Lake Tahoe,
CA,
USA
25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings.
IEEE 2007, ISBN 1-4244-1258-7 BibTeX
Signal Processing Circuits
Advances in Verification
Novel Memory and Communication Subsystems
Variation Aware Design Methodologies
- Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu:
Analytical thermal placement for VLSI lifetime improvement and minimum performance variation.
71-77
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- Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan:
Voltage drop reduction for on-chip power delivery considering leakage current variations.
78-83
Electronic Edition (link) BibTeX
- Aswin Sreedhar, Sandip Kundu:
On modeling impact of sub-wavelength lithography on transistors.
84-90
Electronic Edition (link) BibTeX
- Cristiano Forzan, Davide Pandini:
Why we need statistical static timing analysis.
91-96
Electronic Edition (link) BibTeX
- Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak:
Statistical timing analysis using Kernel smoothing.
97-102
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Tutorial:
Software-Defined Radio (SDR) Technology
Microarchitecture,
Multiprocessors and Systems-on-chip
FPGA Architecture and Design
Application-Optimized Architectures
- Liang-Kai Wang, Charles Tsen, Michael J. Schulte, Divya Jhalani:
Benchmarks and performance analysis of decimal floating-point applications.
164-170
Electronic Edition (link) BibTeX
- Yoshiyuki Kaeriyama, Daichi Zaitsu, Ken-ichi Suzuki, Hiroaki Kobayashi, Nobuyuki Ohba:
Multi-core data streaming architecture for ray tracing.
171-178
Electronic Edition (link) BibTeX
- David Meisner, Sherief Reda:
Hardware libraries: An architecture for economic acceleration in soft multi-core environments.
179-186
Electronic Edition (link) BibTeX
- Hai Lin, Xuan Guan, Yunsi Fei, Zhijie Jerry Shi:
Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors.
187-193
Electronic Edition (link) BibTeX
Three-Dimensional Integrated Circuits
- Lili Zhou, Cherry Wakayama, Robin Panda, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi:
Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits.
194-201
Electronic Edition (link) BibTeX
- Phil Jacobs, Aamir Zia, Okan Erdogan, Paul M. Belemjian, Peng Jin, Jin Woo Kim, Michael Chu, Russell P. Kraft, John F. McDonald:
Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking.
202-207
Electronic Edition (link) BibTeX
- Xiaoxia Wu, Paul Falkenstern, Yuan Xie:
Scan chain design for three-dimensional integrated circuits (3D ICs).
208-214
Electronic Edition (link) BibTeX
Industry Challenges in Wireless Communication
Cache memory architecture (I)
- Hyunjin Lee, Sangyeun Cho, Bruce R. Childers:
Exploring the interplay of yield, area, and performance in processor caches.
216-223
Electronic Edition (link) BibTeX
- Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan:
Improving the reliability of on-chip L2 cache using redundancy.
224-229
Electronic Edition (link) BibTeX
- Houman Homayoun, Alexander V. Veidenbaum:
Reducing leakage power in peripheral circuits of L2 caches.
230-237
Electronic Edition (link) BibTeX
- Fei Gao, Hanyu Cui, Suleyman Sair:
Two-level ata prefetching.
238-244
Electronic Edition (link) BibTeX
- Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras:
Cache replacement based on reuse-distance prediction.
245-250
Electronic Edition (link) BibTeX
Novel Techniques in Physical Design
- Huan Ren, Shantanu Dutt:
Constraint satisfaction in incremental placement with application to performance optimization under power constraints.
251-258
Electronic Edition (link) BibTeX
- Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong:
Fine grain 3D integration for microarchitecture design through cube packing exploration.
259-266
Electronic Edition (link) BibTeX
- Eric Wong, Sung Kyu Lim:
Whitespace redistribution for thermal via insertion in 3D stacked ICs.
267-272
Electronic Edition (link) BibTeX
- Mohit Pathak, Souvik Mukherjee, Madhavan Swaminathan, Ege Engin, Sung Kyu Lim:
Placement and routing of RF embedded passive designs in LCP substrate.
273-279
Electronic Edition (link) BibTeX
Arithmetic Circuits
- Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi:
A radix-10 SRT divider based on alternative BCD codings.
280-287
Electronic Edition (link) BibTeX
- Charles Tsen, Sonia Gonzalez-Navarro, Michael J. Schulte:
Hardware design of a Binary Integer Decimal-based floating-point adder.
288-295
Electronic Edition (link) BibTeX
- Brian J. Hickmann, Andrew Krioukov, Michael J. Schulte, Mark A. Erle:
A parallel IEEE P754 decimal floating-point multiplier.
296-303
Electronic Edition (link) BibTeX
- Michael J. Schulte, Dimitri Tan, Carl Lemonds:
Floating-point division algorithms for an x86 microprocessor with a rectangular multiplier.
304-310
Electronic Edition (link) BibTeX
- Gongqiong Li, Zhaolin Li:
Optimized design of a double-precision floating-point multiply-add-dused unit for data dependence.
311-316
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Reliability and fault tolerance
Novel Test Techniques
Low Power Design
- Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki:
An automated runtime power-gating scheme.
382-387
Electronic Edition (link) BibTeX
- Ku He, Rong Luo, Yu Wang:
A power gating scheme for ground bounce reduction during mode transition.
388-394
Electronic Edition (link) BibTeX
- Yoonjin Kim, Rabi N. Mahapatra:
Dynamically compressible context architecture for low power coarse-grained reconfigurable array.
395-400
Electronic Edition (link) BibTeX
- Sheng Sun, Carl Sechen:
Post-layout comparison of high performance 64b static adders in energy-delay space.
401-408
Electronic Edition (link) BibTeX
Power and thermal considerations in processor design
Circuit Design and Simulation
- Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen:
A technique for selecting CMOS transistor orders.
438-443
Electronic Edition (link) BibTeX
- Veerapaneni Nagbhushan, C. Y. Roger Chen:
Algorithms to simplify multi-clock/edge timing constraints.
444-449
Electronic Edition (link) BibTeX
- Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen:
An efficient gate delay model for VLSI design.
450-455
Electronic Edition (link) BibTeX
- Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng:
Fast power network analysis with multiple clock domains.
456-463
Electronic Edition (link) BibTeX
Simulation and Scheduling
Cache memory architecture
RF and Analog Test
Synchronization and Interconnect
Design Techniques for Emerging Technologies
System Level and Architectural Synthesis
Process-aware Design:
Power,
Thermal and Reliability
- Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya:
Power reduction of chip multi-processors using shared resource control cooperating with DVFS.
615-622
Electronic Edition (link) BibTeX
- Inchoon Yeo, Heung Ki Lee, Eun Jung Kim, Ki Hwan Yum:
Effective Dynamic Thermal Management for MPEG-4 decoding.
623-628
Electronic Edition (link) BibTeX
- Dakai Zhu, Xuan Qi, Hakan Aydin:
Priority-monotonic energy management for real-time systems with reliability requirements.
629-635
Electronic Edition (link) BibTeX
- Ming Su, Lili Zhou, C.-J. Richard Shi:
Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining.
636-643
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:16:36 2009
by Michael Ley (ley@uni-trier.de)
