ISSS 2001:
Montréal,
Québec,
Canada
International Symposium on Systems Synthesis,
ISSS 2001,
Montréal,
Québec,
Canada,
September 30 - October 3,
2001,
Proceedings. ACM,
2001
Memory optimization methodologies
- Om Prakash Gangwal, André Nieuwland, Paul E. R. Lippens:
A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems.
1-6 BibTeX
- Mahmut T. Kandemir, Ismail Kadayif, Ugur Sezer:
Exploiting scratch-pad memory using Presburger formulas.
7-12 BibTeX
- Tycho van Meeuwen, Arnout Vandecappelle, Allert van Zelst, Francky Catthoor, Diederik Verkest:
System-level interconnect architecture exploration for custom memory organizations.
13-18 BibTeX
- Samy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya:
An optimal memory allocation for application-specific multiprocessor system-on-chip.
19-24 BibTeX
- Peter Grun, Nikil D. Dutt, Alexandru Nicolau:
APEX.
25-32 BibTeX
Keynote
H/S Embedded Systems
- Kaiyu Chen, Sharad Malik, David I. August:
Retargetable static timing analysis for embedded software.
39-44 BibTeX
- Per Bjuréus, Axel Jantsch:
Performance analysis with confidence intervals for embedded software processes.
45-50 BibTeX
- Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto:
On-line fault detection in a hardware/software co-design environment.
51-56 BibTeX
- Gunnar Braun, Andreas Hoffmann, Achim Nohl, Heinrich Meyr:
Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description.
57-62 BibTeX
- Haris Lekatsas, Jörg Henkel, Wayne Wolf:
Design and simulation of a pipelined decompression architecture for embedded systems.
63-68 BibTeX
Special Session on Design Paradigms
Panel
Memory aspects in system design
- Antoine Fraboulet, Karen Kodary, Anne Mignotte:
Loop fusion for memory space optimization.
95-100 BibTeX
- Preeti Ranjan Panda, Luc Séméria, Giovanni De Micheli:
Cache-efficient memory layout of aggregate data structures.
101-106 BibTeX
- Miguel Miranda, C. Ghez, Chidamber Kulkarni, Francky Catthoor, Diederik Verkest:
Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications.
107-112 BibTeX
- Peter Petrov, Alex Orailoglu:
Data cache energy minimizations through programmable tag size matching to the applications.
113-117 BibTeX
- Marco Bekooij, Jochen A. G. Jess, Jef L. van Meerbergen:
Phase coupled operation assignment for VLIW processors with distributed register files.
118-123 BibTeX
Synthesis for Low Power
- Lama H. Chandrasena, Priyadarshana Chandrasena, Michael J. Liebelt:
An energy efficient rate selection algorithm for voltage quantized dynamic voltage scaling.
124-129 BibTeX
- Radu Muresan, Catherine H. Gebotys:
Current consumption dynamics at instruction and program level for a VLIW DSP processor.
130-135 BibTeX
- Giovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni:
Dynamic modeling of inter-instruction effects for execution time estimation.
136-141 BibTeX
- Ansgar Stammermann, Lars Kruse, Wolfgang Nebel, Alexander Pratsch, Eike Schmidt, Milan Schulte, Arne Schulz:
System level optimization and design space exploration for low power.
142-146 BibTeX
- Kyu-won Choi, Abhijit Chatterjee:
Efficient instruction-level optimization methodology for low-power embedded systems.
147-152 BibTeX
- Eui-Young Chung, Luca Benini, Giovanni De Micheli:
Source code transformation based on software cost analysis.
153-158 BibTeX
High Level and Architectural Synthesis
- Qin Zhao, Twan Basten, Bart Mesman, C. A. J. van Eijk, Jochen A. G. Jess:
Static resource models of instruction sets.
159-164 BibTeX
- Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay:
Combined instruction and loop parallelism in array synthesis for FPGAs.
165-170 BibTeX
- Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau:
Conditional speculation and its effects on performance and area for high-level snthesis.
171-176 BibTeX
- Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh:
A data scheduler for multi-context reconfigurable architectures.
177-182 BibTeX
- Zhong Wang, Qingfeng Zhuge, Edwin Hsing-Mean Sha:
Scheduling and partitioning for multiple loop nests.
183-188 BibTeX
- Tommy Kuhn, Tobias Oppold, C. Schulz-Key, Markus Winterholer, Wolfgang Rosenstiel, Mark Edwards, Yaron Kashai:
Object oriented hardware synthesis and verification.
189-194 BibTeX
Special Session on Network Processors:
An Industrial Perspective
Panel
IP Design and Reuse
Formal Aspects and Distributed Systems
- Ying Zhao, Sharad Malik, Matthew W. Moskewicz, Conor F. Madigan:
Accelerating boolean satisfiability through application specific processing.
244-249 BibTeX
- Marcus T. Schmitz, Bashir M. Al-Hashimi:
Considering power variations of DVS processing elements for energy minimisation in distributed systems.
250-255 BibTeX
- Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau:
Functional abstraction driven design space exploration of heterogeneous programmable architectures.
256-261 BibTeX
- JoAnn M. Paul, Arne J. Suppé, Donald E. Thomas:
Modeling and simulation of steady state and transient behaviors for emergent SoCs.
262-267 BibTeX
- Ahmed Khoumsi:
Synthesizing distributed real-time systems modeled by a timed version of a subset of LOTOS.
268-273 BibTeX
- Abhijit K. Deb, Johnny Öberg, Axel Jantsch:
Control and communication performance analysis of embedded DSP systems in the MASIC methodology.
274-273 BibTeX
Copyright © Sat May 16 23:26:25 2009
by Michael Ley (ley@uni-trier.de)
