23. DAC 1986:
Las Vegas,
Nevada,
USA
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas,
NV,
June 1986. IEEE Computer Society Press,
1986
- Robert M. Williams:
IBM perspectives on the electrical design automation industry (keynote address).
1
Electronic Edition (ACM DL) BibTeX
- Robert J. Smith II:
Fundamentals of parallel logic simulation.
2-12
Electronic Edition (ACM DL) BibTeX
- Kenneth F. Wong, Mark A. Franklin, Roger D. Chamberlain, B. L. Shing:
Statistics on logic simulation.
13-19
Electronic Edition (ACM DL) BibTeX
- Edward H. Frank:
Exploiting parallelism in a switch-level simulation machine.
20-26
Electronic Edition (ACM DL) BibTeX
- Randy H. Katz, M. Anwarrudin, Ellis E. Chang:
A version server for computer-aided design data.
27-33
Electronic Edition (ACM DL) BibTeX
- Dominique Rieu, Gia Toan Nguyen:
Semantics of CAD objects for generalized databases.
34-40
Electronic Edition (ACM DL) BibTeX
- Shlomo Weiss, Katie Rotzell, Tom Rhyne, Arny Goldfein:
DOSS: a storage system for design data.
41-47
Electronic Edition (ACM DL) BibTeX
- David Knapp, Alice C. Parker:
A design utility manager: the ADAM planning engine.
48-54
Electronic Edition (ACM DL) BibTeX
- Michael L. Bushnell, Stephen W. Director:
VLSI CAD tool integration using the Ulysses environment.
55-61
Electronic Edition (ACM DL) BibTeX
- Forrest Brewer, Daniel Gajski:
An expert-system paradigm for design.
62-68
Electronic Edition (ACM DL) BibTeX
- J. M. Hancock, S. DasGupta:
Tutorial on parallel processing for design automation applications (tutorial session).
69-77
Electronic Edition (ACM DL) BibTeX
- Aart J. de Geus:
Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference.
78
Electronic Edition (ACM DL) BibTeX
- David Gregory, Karen A. Bartlett, Aart J. de Geus, Gary D. Hachtel:
SOCRATES: a system for automatically synthesizing and optimizing combinational logic.
79-85
Electronic Edition (ACM DL) BibTeX
- Tsutomu Sasao:
MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators.
86-93
Electronic Edition (ACM DL) BibTeX
- William H. Joyner Jr., Louise Trevillyan, Daniel Brand, Theresa A. Nix, Steven C. Gundersen:
Technology adaption in logic synthesis.
94-100
Electronic Edition (ACM DL) BibTeX
- D. F. Wong, C. L. Liu:
A new algorithm for floorplan design.
101-107
Electronic Edition (ACM DL) BibTeX
- Jayaram Bhasker, Sartaj Sahni:
A linear algorithm to find a rectangular dual of a planar triangulated graph.
108-114
Electronic Edition (ACM DL) BibTeX
- Hyunchul Shin, Alberto L. Sangiovanni-Vincentelli, Carlo H. Séquin:
Two-dimensional compaction by ``zone refining''.
115-122
Electronic Edition (ACM DL) BibTeX
- Sching L. Lin, Jonathan Allen:
Minplex - a compactor that minimizes the bounding rectangle and individual rectangles in a layout.
123-130
Electronic Edition (ACM DL) BibTeX
- Venkat V. Venkataraman, Craig D. Wilcox:
GEMS: an automatic layout tool for MIMOLA schematics.
131-137
Electronic Edition (ACM DL) BibTeX
- Akira Sugimoto, Shigeru Abe, Masahiro Kuroda, Yukio Kato:
An object-oriented visual simulator for microprogram development.
138-144
Electronic Edition (ACM DL) BibTeX
- Alberto Di Janni:
A monitor for complex CAD systems.
145-151
Electronic Edition (ACM DL) BibTeX
- Katherine Hammer, Dan Radin, Tom Rhyne, John Hardin, Tina Timmerman:
Automating the generation of interactive interfaces.
152-158
Electronic Edition (ACM DL) BibTeX
- Dan Adler:
SIMMOS: a multiple-delay switch-level simulator.
159-163
Electronic Edition (ACM DL) BibTeX
- Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman:
SLS - a fast switch level simulator for verification and fault coverage analysis.
164-170
Electronic Edition (ACM DL) BibTeX
- William S. Beckett:
MOS circuit models in Network C.
171-178
Electronic Edition (ACM DL) BibTeX
- Luís M. Vidigal, Sani R. Nassif, Stephen W. Director:
CINNAMON: coupled integration and nodal analysis of MOS networks.
179-185
Electronic Edition (ACM DL) BibTeX
- Peter Odryna, Kevin Nazareth, Carl Christensen:
A workstation-mixed model circuit simulator.
186-192
Electronic Edition (ACM DL) BibTeX
- Y. S. Kuo, W. K. Chou:
Generating essential primes for a Boolean function with multiple-valued inputs.
193-199
Electronic Edition (ACM DL) BibTeX
- Kenneth J. Supowit, Steven J. Friedman:
A new method for verifying sequential circuits.
200-207
Electronic Edition (ACM DL) BibTeX
- Gotaro Odawara, Masahiro Tomita, Osamu Okuzawa, Tomomichi Ohta, Zhen-quan Zhuang:
A logic verifier based on Boolean comparison.
208-214
Electronic Edition (ACM DL) BibTeX
- S. Bapat, G. Venkatesh:
Reasoning about digital systems using temporal logic.
215-219
Electronic Edition (ACM DL) BibTeX
- Manfred Glesner, Johannes Schuck, R. B. Steck:
SCAT - a new statistical timing verifier in a silicon compiler system.
220-226
Electronic Edition (ACM DL) BibTeX
- Seung Ho Hwang, Young Hwan Kim, A. Richard Newton:
An accuration delay modeling technique for switch-level timing verification.
227-233
Electronic Edition (ACM DL) BibTeX
- Andrzej J. Strojwas, Clark Beck, Dennis Buss, Tülin Erdim Mangir, Charles H. Stapper:
Yield of VLSI circuits: myths vs. reality (panel).
234-235
Electronic Edition (ACM DL) BibTeX
- Weiwei Mao, Xieting Ling:
Robust test generation algorithm for stuck-open fault in CMOS circuits.
236-242
Electronic Edition (ACM DL) BibTeX
- Hsi-Ching Shih, Jacob A. Abraham:
Transistor-level test generation for physical failures in CMOS circuits.
243-249
Electronic Edition (ACM DL) BibTeX
- Ralph Marlett:
An effective test generation system for sequential circuits.
250-256
Electronic Edition (ACM DL) BibTeX
- Daniel S. Barclay, James R. Armstrong:
A heuristic chip-level test generation algorithm.
257-262
Electronic Edition (ACM DL) BibTeX
- Pierre G. Paulin, John P. Knight, Emil F. Girczyc:
HAL: a multi-paradigm approach to automatic data path synthesis.
263-270
Electronic Edition (ACM DL) BibTeX
- Peter Marwedel:
A new synthesis for the MIMOLA software system.
271-277
Electronic Edition (ACM DL) BibTeX
- Zebo Peng:
Synthesis of VLSI systems with the CAMAD design aid.
278-284
Electronic Edition (ACM DL) BibTeX
- R. Brück, Bernd Kleinjohann, Thomas Kathöfer, Franz J. Rammig:
Synthesis of concurrent modular controllers from algorithmic descriptions.
285-292
Electronic Edition (ACM DL) BibTeX
- Surendra Nahar, Sartaj Sahni, Eugene Shragowitz:
Simulated annealing and combinatorial optimization.
293-299
Electronic Edition (ACM DL) BibTeX
- Antoni A. Szepieniec:
Integrated placement/routing in sliced layouts.
300-307
Electronic Edition (ACM DL) BibTeX
- Knut M. Just, Jürgen M. Kleinhans, Frank M. Johannes:
On the relative placement and the transportation problem for standard-cell layout.
308-313
Electronic Edition (ACM DL) BibTeX
- Mark R. Hartoog:
Analysis of placement procedures for VLSI standard cell layout.
314-319
Electronic Edition (ACM DL) BibTeX
- Moe Shahdad:
An overview of VHDL language and technology.
320-326
Electronic Edition (ACM DL) BibTeX
- John P. Eurich:
A tutorial introduction to the electronic design interchange format (tutorial session).
327-333
Electronic Edition (ACM DL) BibTeX
- Wilfried Daehn:
A unified treatment of PLA faults by Boolean differences.
334-338
Electronic Edition (ACM DL) BibTeX
- Michiel M. Ligthart, Emile H. L. Aarts, Frans P. M. Beenker:
Design-for-testability of PLA's using statistical cooling.
339-345
Electronic Edition (ACM DL) BibTeX
- M. Ladjadj, J. F. McDonald, D.-H. Ho, W. Murray:
Use of the subscripted DALG in submodule testing with applications in cellular arrays.
346-353
Electronic Edition (ACM DL) BibTeX
- Yasuhiro Ohno, Masayuki Miyoshi, Norio Yamada, Toshihiko Odaka, Tokinori Kozawa, Kooichiro Ishihara:
Principles of design automatioon system for very large scale computer design.
354-359
Electronic Edition (ACM DL) BibTeX
- Masayuki Miyoshi, Yoshio Ooshima, Atsushi Sugiyama, Nobuhiko Onizuka, Nobutaka Amano:
An extensive logic simulation method of very large scale computer design.
360-365
Electronic Edition (ACM DL) BibTeX
- Yooji Tsuchiya, Masato Morita, Yukio Ikariya, Eiichi Tsurumi, Teruo Mori, Tamoatsu Yanagita:
Establishment of higher level logic design for very large scale computer.
366-371
Electronic Edition (ACM DL) BibTeX
- Roger J. Pachter, R. Smith, Ronald Waxman, J. Hines, H. G. Adhead, L. O'Connell, M. Shahdad, John P. Eurich:
Computer aided (CA) tools integration and related standards development (panel session).
372-373
Electronic Edition (ACM DL) BibTeX
- David R. Tryon:
Self-testing with correlated faults.
374-377
Electronic Edition (ACM DL) BibTeX
- Gerd Krüger:
Automatic generation of self-test programs - a new feature of the MIMOLA design system.
378-384
Electronic Edition (ACM DL) BibTeX
- Sy-Yen Kuo, W. Kent Fuchs:
Efficient spare allocation in reconfigurable arrays.
385-390
Electronic Edition (ACM DL) BibTeX
- T. Shinsha, T. Kubo, Y. Sakataya, J. Koshishita, K. Ishihara:
Incremental logic synthesis through gate logic structure identification.
391-397
Electronic Edition (ACM DL) BibTeX
- Reiji Toyoshima, Yoshimitsu Takiguchi, Kazumi Matsumoto, Hidetomo Hongou, Mashiro Hashimoto, Ryotaro Kamikawai, Katsuhiko Takizawa:
An effective delay analysis system for a large scale computer design.
398-403
Electronic Edition (ACM DL) BibTeX
- Yasushi Ogawa, Tatsuki Ishii, Yoichi Shiraishi, Hidekazu Terai, Tokinori Kozawa, Kyoji Yuyama, Kyoji Chiba:
Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs.
404-410
Electronic Edition (ACM DL) BibTeX
- Surendra Nahar, Sartaj Sahni:
A time and space efficient net extractor.
411-417
Electronic Edition (ACM DL) BibTeX
- R. D. Freeman, S. M. Kang, C. G. Lin-Hendel, M. L. Newby:
Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning.
418-424
Electronic Edition (ACM DL) BibTeX
- Ahsan Bootehsaz, Robert A. Cottrel:
A technology independent approach to hierarchical IC layout extraction.
425-431
Electronic Edition (ACM DL) BibTeX
- Carl Sechen, Alberto L. Sangiovanni-Vincentelli:
TimberWolf3.2: a new standard cell placement and global routing package.
432-439
Electronic Edition (ACM DL) BibTeX
- Peter S. Hauge, Ellen J. Yoffa:
Vanguard: a chip physical design system.
440-446
Electronic Edition (ACM DL) BibTeX
- David E. Krekelberg, Eugene Shragowitz, Gerald E. Sobelman, Li-Shin Lin:
Automated layout synthesis in the YASC silicon compiler.
447-453
Electronic Edition (ACM DL) BibTeX
- Nohbyung Park, Alice C. Parker:
Sehwa: a program for synthesis of pipelines.
454-460
Electronic Edition (ACM DL) BibTeX
- Alice C. Parker, Jorge T. Pizarro, Mitch J. Mlinar:
MAHA: a program for datapath synthesis.
461-466
Electronic Edition (ACM DL) BibTeX
- Fadi J. Kurdahi, Alice C. Parker:
PLEST: a program for area estimation of VLSI integrated circuits.
467-473
Electronic Edition (ACM DL) BibTeX
- Michael C. McFarland:
Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions.
474-480
Electronic Edition (ACM DL) BibTeX
- W. K. Luk, Donald T. Tang, C. K. Wong:
Hierarchial global wiring for custom chip design.
481-489
Electronic Edition (ACM DL) BibTeX
- Charles H. Ng:
An industrial world channel router for non-rectangular channels.
490-494
Electronic Edition (ACM DL) BibTeX
- Douglas Braun, Jeffrey L. Burns, Srinivas Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli:
Chameleon: a new multi-layer channel router.
495-502
Electronic Edition (ACM DL) BibTeX
- Alex Orailoglu, Daniel Gajski:
Flow graph representation.
503-509
Electronic Edition (ACM DL) BibTeX
- Júlio S. Aude, Hilary J. Kahn:
A design rule database system to support technology-adaptable applications.
510-516
Electronic Edition (ACM DL) BibTeX
- John Ivie, Kwok-Woon Larry Lai:
STL - a high level language for simulation and test.
517-523
Electronic Edition (ACM DL) BibTeX
- Jon A. Solworth:
GENERIC: a silicon compiler support language.
524-530
Electronic Edition (ACM DL) BibTeX
- William P. Birmingham, Rostam Joobbani, Jin Kim:
Knowlege-based expert systems and their application (tutorial session.
531-539
Electronic Edition (ACM DL) BibTeX
- Hans-Joachim Wunderlich, Wolfgang Rosenstiel:
On fault modeling for dynamic MOS circuits.
540-546
Electronic Edition (ACM DL) BibTeX
- Sanjay J. Patel, Janak H. Patel:
Effectiveness of heuristics measures for automatic test pattern generation.
547-552
Electronic Edition (ACM DL) BibTeX
- Hi-Keung Tony Ma, Alberto L. Sangiovanni-Vincentelli:
Mixed-level fault coverage estimation.
553-559
Electronic Edition (ACM DL) BibTeX
- Wojciech Maly:
Optimal order of the VLSI IC testing sequence.
560-566
Electronic Edition (ACM DL) BibTeX
- Saul A. Kravitz, Rob A. Rutenbar:
Multiprocessor-based placement by simulated annealing.
567-573
Electronic Edition (ACM DL) BibTeX
- Takumi Watanabe, Yoshi Sugiyama:
A new routing algorithm and its hardware implementation.
574-580
Electronic Edition (ACM DL) BibTeX
- Shigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Hiroshi Ishikura, Nobuhiko Koike:
HAL II: a mixed level hardware logic simulation system.
581-587
Electronic Edition (ACM DL) BibTeX
- George K. Jacob, A. Richard Newton, Donald O. Pederson:
An empirical analysis of the performance of a multiprocessor-based circuit simulator.
588-593
Electronic Edition (ACM DL) BibTeX
- Takao Saito, Hiroyuki Sugimoto, Masami Yamazaki, Nobuaki Kawato:
A rule-based logic circuit synthesis system for CMOS gate arrays.
594-600
Electronic Edition (ACM DL) BibTeX
- Hiroyuki Watanabe, Bryan D. Ackland:
Flute - a floorplanning agent for full custom VLSI design.
601-607
Electronic Edition (ACM DL) BibTeX
- T. Watanabe, T. Masuishi, T. Nishiyama, N. Horie:
Knowledge-based optimal IIL generator from conventional logic circuit descriptions.
608-614
Electronic Edition (ACM DL) BibTeX
- Edward J. DeJesus, James P. Callan, Curtis R. Whitehead:
PEARL: an expert system for power supply layout.
615-621
Electronic Edition (ACM DL) BibTeX
- Bryan Preas, Patrick G. Karger:
Automatic placement a review of current techniques (tutorial session).
622-629
Electronic Edition (ACM DL) BibTeX
- Howard S. Rifkin, William Heller, Steve Law, Misha Burich, Alberto L. Sangiovanni-Vincentelli:
Floor planning systems (panel session).
630
Electronic Edition (ACM DL) BibTeX
- Srinivas Devadas, A. Richard Newton:
GENIE: a generalized array optimizer for VLSI synthesis.
631-637
Electronic Edition (ACM DL) BibTeX
- Christine M. Gerveshi:
Comparison of CMOS PLA and polycell representations of control logic.
638-642
Electronic Edition (ACM DL) BibTeX
- Alan J. Coppola:
An implementation of a state assignment heuristic.
643-649
Electronic Edition (ACM DL) BibTeX
- Edmund M. Clarke, Yulin Feng:
Escher - a geometrical layout system for recursively defined circuits.
650-653
Electronic Edition (ACM DL) BibTeX
- Patrice Frison, Eric Gautrin:
MADMACS: a new VLSI layout macro editor.
654-658
Electronic Edition (ACM DL) BibTeX
- Antony P.-C. Ng, Clark D. Thompson, Prabhakar Raghavan:
A language for describing rectilinear Steiner tree configurations.
659-662
Electronic Edition (ACM DL) BibTeX
- S. K. Nandy, L. V. Ramakrishnan:
Dual quadtree representation for VLSI designs.
663-666
Electronic Edition (ACM DL) BibTeX
- Richard H. Lathrop, Robert S. Kirk:
Precedent-based manipulation of VLSI structures.
667-670
Electronic Edition (ACM DL) BibTeX
- W. Stephen Adolph, Hassan K. Reghbati, Amar Sanmugasunderam:
A frame based system for representing knowledge about VLSI design: a proposal.
671-676
Electronic Edition (ACM DL) BibTeX
- Sumit Ghosh:
A rule-based approach to unifying functional and fault simulation and timing verification.
677-682
Electronic Edition (ACM DL) BibTeX
- David E. Wallace, Carlo H. Séquin:
Plug-in timing models for an abstract timing verifier.
683-689
Electronic Edition (ACM DL) BibTeX
- Jonathan D. Pincus, Alvin M. Despain:
Delay reduction using simulated annealing.
690-695
Electronic Edition (ACM DL) BibTeX
- J. Fernando Naveda, K. C. Chang, David Hung-Chang Du:
A new approach to multi-layer PCB routing with short vias.
696-701
Electronic Edition (ACM DL) BibTeX
- K. C. Chang, David Hung-Chang Du:
A preprocessor for the via minimization problem.
702-707
Electronic Edition (ACM DL) BibTeX
- Richard J. Enbody, David Hung-Chang Du:
Near-optimal n-layer channel routing.
708-714
Electronic Edition (ACM DL) BibTeX
- Ahmed Amine Jerraya, P. Varinot, R. Jamier, Bernard Courtois:
Principles of the SYCO compiler.
715-721
Electronic Edition (ACM DL) BibTeX
- Tom Marshburn, Ivy Lui, Rick Brown, Dan Cheung, Gary Lum, Peter Cheng:
DATAPATH: a CMOS data path silicon assembler.
722-729
Electronic Edition (ACM DL) BibTeX
- Paul Six, Luc J. M. Claesen, Jan M. Rabaey, Hugo De Man:
An intelligent module generator environment.
730-735
Electronic Edition (ACM DL) BibTeX
- Rathin Putatunda, David Smith, Stephen McNeary, James Crabbe:
HAPPI: a chip compiler based on double-level-metal technology.
736-743
Electronic Edition (ACM DL) BibTeX
- Wayne Wolf:
An object-oriented, procedural database for VLSI chip planning.
744-751
Electronic Edition (ACM DL) BibTeX
- J. Gonzalez-Sustaeta, Alejandro P. Buchmann:
An automated database design tool using the ELKA conceptual model.
752-759
Electronic Edition (ACM DL) BibTeX
- Christian Jullien, Andre Leblond, Jacques Lecourvoisier:
A database interface for an integrated CAD system.
760-767
Electronic Edition (ACM DL) BibTeX
- Robert P. Larsen:
Rules-based object clustering: a data structure for symbolic VLSI synthesis and analysis.
768-777
Electronic Edition (ACM DL) BibTeX
- Robert E. Canright:
Simulating and controlling the effects of transmission line impedance mismatches.
778-785
Electronic Edition (ACM DL) BibTeX
- Kuniaki Kishida, F. Shirotori, Y. Ikemoto, Shun Ishiyama, Terumine Hayashi:
A delay test system for high speed logic LSI's.
786-790
Electronic Edition (ACM DL) BibTeX
- Toshihiko Tada, Akihiko Hanafusa:
Router system for printed wiring boards of very high-speed, very large-scale computers.
791-797
Electronic Edition (ACM DL) BibTeX
- John Kessenich, Gary Jackoway:
Global forced hierarchical router.
798-802
Electronic Edition (ACM DL) BibTeX
- Kaoru Kawamura, Masanobu Umeda, Hiroshi Shiraishi:
Hierarchical dynamic router.
803-809
Electronic Edition (ACM DL) BibTeX
- Vijay S. Bobba, J. W. Smith:
A parameter-driven router.
810-818
Electronic Edition (ACM DL) BibTeX
- Pat Lamey:
Early verification of prototype tooling for IC designs.
819-822
Electronic Edition (ACM DL) BibTeX
- J. G. Xiong:
Algorithms for global routing.
824-830
Electronic Edition (ACM DL) BibTeX
Copyright © Sat May 16 23:04:34 2009
by Michael Ley (ley@uni-trier.de)
