24. MICRO 1991:
Albuquerque,
New Mexico,
USA
MICRO 24,
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture,
November 18-20,
1991,
Albuquerque,
New Mexico,
USA
- Michael A. Schuette, John Paul Shen:
An Instruction-Level Performance Analysis of the Multiflow TRACE 14/300.
2-11
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- William Marcus Miller, Walid A. Najjar, A. P. Wim Böhm:
A Quantitative Analysis of Locality in Dataflow Programs.
12-18
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- Jeffrey C. Becker, Arvin Park, Matthew K. Farrens:
An Analysis of the Information Content of Address Reference Streams.
19-24
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- Pohua P. Chang, William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu:
Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors.
25-33
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- Michael Butler, Yale N. Patt:
The Effect of Real Data Cache Behavior on the Performance of a Microarchitecture that Supports Dynamic Scheduling.
34-41
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- Brian K. Bray, Michael J. Flynn:
Strategies for Branch Target Buffers.
42-50
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- Tse-Yu Yeh, Yale N. Patt:
Two-Level Adaptive Training Branch Prediction.
51-61
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- Matthew K. Farrens, Arvin Park:
Workload and Implementation Considerations for Dynamic Base Register Caching.
62-68
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- William Y. Chen, Scott A. Mahlke, Pohua P. Chang, Wen-mei W. Hwu:
Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching.
69-73
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- Jan Hoogerbrugge, Henk Corporaal, Hans Mulder:
Software Pipelining for Transport-Triggered Architectures.
74-81
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- Reese B. Jones, Vicki H. Allan:
Software Pipelining: An Evaluation of Enhanced Pipelining.
82-92
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- Mark Smotherman, Sanjay Krishnamurthy, P. S. Aravind, David Hunnicutt:
Efficient DAG Construction and Heuristic Calculation for Instruction Scheduling.
93-102
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- David Bernstein, Doron Cohen, Hugo Krawczyk:
Code Duplication: An Assist for Global Instruction Scheduling.
103-113
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- Mauricio Breternitz Jr., John Paul Shen:
Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors.
114-123
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- Ramesh Karri, Alex Orailoglu:
ALPS: An Algorithm for Pipeline Data Path Synthesis.
124-132
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- Robert A. Walker, Shivkumar Ramabadran, Rajive Joshi, Steinar Flatland:
Increasing User Interaction During High-Level Synthesis.
133-142
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- Gautam B. Singh:
GRIP: Graphics Reduced Instruction Processor.
143-152
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- Bruce K. Holmer, Alvin M. Despain:
Viewing Instruction Set Design as an Optimization Problem.
153-162
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- Mario Nemirovsky, Forrest Brewer, Roger C. Wood:
DISC: Dynamic Instruction Stream Computer.
163-171
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- Haigeng Wang, Alexandru Nicolau, Roni Potasman:
A New Technique for Induction Variable Removal.
172-180
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- Gerben Essink, Emile H. L. Aarts, R. van Dongen, P. van Gerwen, Jan H. M. Korst, Kees A. Vissers:
Architecture and Programming of a VLIW Style Programmable Video Signal Processor.
181-188
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- Fredrik Dahlgren, Per Stenström:
On Reconfigurable On-Chip Data Caches.
189-198
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- Sunah Lee, Rajiv Gupta:
Executing Loops on a Fine-Grained MIMD Architecture.
199-205
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- Steven J. Beaty:
Genetic Algorithms and Instruction Scheduling.
206-211
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- Bogong Su, Jian Wang:
GURPR*: A New Global Software Pipelining Algorithm.
212-216
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- Samarina Makhdoom, Daniel Tabak, Richard Auletta:
Register/File/Cache Microarchitecture Study Using VHDL.
217-222
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Copyright © Sat May 16 23:29:53 2009
by Michael Ley (ley@uni-trier.de)