Volume 40,
Number 1,
January 2007
Embedded Cryptographic Hardware
- Nadia Nedjah, Luiza de Macedo Mourelle:
Embedded cryptographic hardware.
1-2
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- Akashi Satoh, Tadanobu Inoue:
ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS.
3-10
Electronic Edition (link) BibTeX
- T. S. Ganesh, Michael T. Frederick, T. S. B. Sudarshan, Arun K. Somani:
Hashchip: A shared-resource multi-hash function processor architecture on FPGA.
11-19
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- François-Xavier Standaert, Gilles Piret, Gaël Rouvroy, Jean-Jacques Quisquater:
FPGA implementations of the ICEBERG block cipher.
20-27
Electronic Edition (link) BibTeX
- Tim Kerins, William P. Marnane, Emanuel M. Popovici:
Versatile hardware architectures for GF(pm) arithmetic in public key cryptography.
28-35
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- Nadia Nedjah, Luiza de Macedo Mourelle:
Efficient and secure cryptographic systems based on addition chains: Hardware design vs. software/hardware co-design.
36-44
Electronic Edition (link) BibTeX
- Alireza Hodjat, Lejla Batina, David Hwang, Ingrid Verbauwhede:
HW/SW co-design of a hyperelliptic curve cryptosystem using a microcode instruction set coprocessor.
45-51
Electronic Edition (link) BibTeX
- Eric Peeters, François-Xavier Standaert, Jean-Jacques Quisquater:
Power and electromagnetic analysis: Improved model, consequences and comparisons.
52-60
Electronic Edition (link) BibTeX
Volume 40,
Number 2,
February 2007
Systems-on-Chip:
Design and Test
- Laurence Tianruo Yang, José G. Delgado-Frias, Yiming Li, Mohammed Y. Niamat, Dimitrios Soudris, Srinivasa Vemuru:
Preface.
61
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- Kyung Tae Do, Young Hwan Kim, Haeng Seon Son:
Timing modeling of latch-controlled sub-systems.
62-73
Electronic Edition (link) BibTeX
- Konstantinos Tatas, George Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis:
Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications.
74-93
Electronic Edition (link) BibTeX
- Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin:
Constrained algorithmic IP design for system-on-chip.
94-105
Electronic Edition (link) BibTeX
- Bill Lin:
Compiling concurrent programs for embedded sequential execution.
106-117
Electronic Edition (link) BibTeX
- Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi:
A new array architecture for signed multiplication using Gray encoded radix-2m operands.
118-132
Electronic Edition (link) BibTeX
- Martin John Burbidge, Jim Tijou:
Towards generic charge-pump phase-locked loop, jitter estimation techniques using indirect on chip methods.
133-148
Electronic Edition (link) BibTeX
- Zahra Sadat Ebadi, Alireza Nasiri Avanaki, Resve Saleh, André Ivanov:
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip.
149-160
Electronic Edition (link) BibTeX
- Hung-Mu Chou, Jam-Wen Lee, Yiming Li:
A floating gate design for electrostatic discharge protection circuits.
161-166
Electronic Edition (link) BibTeX
- Deshanand P. Singh, Stephen Dean Brown:
An area-efficient timing closure technique for FPGAs using Shannon's expansion.
167-173
Electronic Edition (link) BibTeX
- Ling Wang, Yingtao Jiang, Henry Selvaraj:
Scheduling and optimal voltage selection with multiple supply voltages under resource constraints.
174-182
Electronic Edition (link) BibTeX
- Sankalp Kallakuri, Alex Doboli, Simona Doboli:
Applying stochastic modeling to bus arbitration for systems-on-chip.
183-191
Electronic Edition (link) BibTeX
Volume 40,
Number 3,
April 2007
- Hui Zhang, Simona Doboli, Hua Tang, Alex Doboli:
Compiled code simulation of analog and mixed-signal systems using piecewise linear modeling of nonlinear parameters: A case study for DeltaSigma modulator simulation.
193-208
Electronic Edition (link) BibTeX
- K. R. Santha, V. Vaidehi:
Design of efficient architectures for 1-D and 2-D DLMS adaptive filters.
209-225
Electronic Edition (link) BibTeX
- Jinjun Xiong, Lei He:
Full-chip multilevel routing for power and signal integrity.
226-234
Electronic Edition (link) BibTeX
- Sotirios G. Ziavras, Alexandros V. Gerbessiotis, Rohan Bafna:
Coprocessor design to support MPI primitives in configurable multiprocessors.
235-252
Electronic Edition (link) BibTeX
- Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu:
An efficient quadratic placement based on search space traversing technology.
253-260
Electronic Edition (link) BibTeX
- Pavel V. Nikitin, C.-J. Richard Shi:
VHDL-AMS based modeling and simulation of mixed-technology microsystems: a tutorial.
261-273
Electronic Edition (link) BibTeX
- Kunihiro Fujiyoshi, Chikaaki Kodama, Akira Ikeda:
A fast algorithm for rectilinear block packing based on selected sequence-pair.
274-284
Electronic Edition (link) BibTeX
- Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti:
BUSpec: A framework for generation of verification aids for standard bus protocol specifications.
285-304
Electronic Edition (link) BibTeX
- Jens Vygen:
New theoretical results on quadratic placement.
305-314
Electronic Edition (link) BibTeX
- Yiorgos Makris, Alex Orailoglu:
On the identification of modular test requirements for low cost hierarchical test path construction.
315-325
Electronic Edition (link) BibTeX
- Krishnan Srinivasan, Karam S. Chatha:
Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints.
326-354
Electronic Edition (link) BibTeX
- Ilham Hassoune, François Macé, Denis Flandre, Jean-Didier Legat:
Dynamic differential self-timed logic families for robust and low-power security ICs.
355-364
Electronic Edition (link) BibTeX
- Sotir Ouzounov, Engel Roza, Hans Hegt, Gerard v. d. Weide, Arthur H. M. van Roermund:
Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption.
365-379
Electronic Edition (link) BibTeX
Volume 40,
Number 4,
July 2007
System-Level Interconnect Prediction
- Igor L. Markov, Louis Scheffer, Dirk Stroobandt:
Special issue on System-Level Interconnect Prediction.
381
Electronic Edition (link) BibTeX
- Wim Heirman, Joni Dambre, I. Artundo, Christof Debaes, Hugo Thienpont, Dirk Stroobandt, Jan M. Van Campenhout:
Predicting reconfigurable interconnect performance in distributed shared-memory systems.
382-393
Electronic Edition (link) BibTeX
- Brajesh Kumar Kaushik, Sankar Sarkar, R. P. Agarwal:
Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load.
394-405
Electronic Edition (link) BibTeX
- Yaoguang Wei, Sheqin Dong, Xianlong Hong:
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement.
406-419
Electronic Edition (link) BibTeX
- Tao Wan, Malgorzata Chrzanowska-Jeske:
A novel net-degree distribution model and its application to floorplanning benchmark generation.
420-433
Electronic Edition (link) BibTeX
- Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman:
Predictions of CMOS compatible on-chip optical interconnect.
434-446
Electronic Edition (link) BibTeX
Regular papers
- João M. S. Silva, L. Miguel Silveira:
Substrate model extraction using finite differences and parallel multigrid.
447-460
Electronic Edition (link) BibTeX
- Magdy A. El-Moursy, Eby G. Friedman:
Wire shaping of RLC interconnects.
461-472
Electronic Edition (link) BibTeX
- Hyun-Sung Kim, Sung-Woon Lee:
LFSR multipliers over GF(2m) defined by all-one polynomial.
473-478
Electronic Edition (link) BibTeX
- Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet:
A fast pipelined multi-mode DES architecture operating in IP representation.
479-489
Electronic Edition (link) BibTeX
- Ming Z. Zhang, Vijayan K. Asari:
An efficient multiplier-less architecture for 2-D convolution with quadrant symmetric kernels.
490-502
Electronic Edition (link) BibTeX
- Jing Huang, Mariam Momenzadeh, Fabrizio Lombardi:
Analysis of missing and additional cell defects in sequential quantum-dot cellular automata.
503-515
Electronic Edition (link) BibTeX
- Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Partitioning-based decoupling capacitor budgeting via sequence of linear programming.
516-524
Electronic Edition (link) BibTeX
- Soumen Maity, Amiya Nayak, S. Ramsundar:
Characterization, testing and reconfiguration of faults in mesh networks.
525-535
Electronic Edition (link) BibTeX
- Omar S. Elkeelany, Ghulam Chaudhry:
Integrating firewire peripheral interface with an ethernet custom network processor.
536-548
Electronic Edition (link) BibTeX
- Mustafa Gök:
A novel IEEE rounding algorithm for high-speed floating-point multipliers.
549-560
Electronic Edition (link) BibTeX
- Vishal Khandelwal, Ankur Srivastava:
Active mode leakage reduction using fine-grained forward body biasing strategy.
561-570
Electronic Edition (link) BibTeX
Copyright © Sun May 17 00:03:50 2009
by Michael Ley (ley@uni-trier.de)
