DFT 2002:
Vancouver,
BC,
Canada
17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings.
IEEE Computer Society 2002, ISBN 0-7695-1831-1 BibTeX
@proceedings{DBLP:conf/dft/2002,
title = {17th IEEE International Symposium on Defect and Fault-Tolerance
in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC,
Canada, Proceedings},
booktitle = {DFT},
publisher = {IEEE Computer Society},
year = {2002},
isbn = {0-7695-1831-1},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Session 1:
Yield I
Session 2:
Crosstalk Faults
Session 3:
Self-Checking and ABFT
- Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri:
A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard.
51-59
Electronic Edition (IEEE Computer Society DL) BibTeX
- Cristiana Bolchini, Fabio Salice, Donatella Sciuto:
Designing Self-Checking FPGAs through Error Detection Codes.
60-68
Electronic Edition (IEEE Computer Society DL) BibTeX
- Jimson Mathew, Elena Dubrova:
Self-Checking 1-out-of-n CMOS Current-Mode Checker.
69-77
Electronic Edition (IEEE Computer Society DL) BibTeX
- Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan:
Partially Duplicated Code-Disjoint Carry-Skip Adder.
78-86
Electronic Edition (IEEE Computer Society DL) BibTeX
- Kartik Mohanram, Nur A. Touba:
Input Ordering in Concurrent Checkers to Reduce Power Consumption.
87-98
Electronic Edition (IEEE Computer Society DL) BibTeX
Session 4:
Fault Simulation and Injection I
Session 5:
Scan Design
Session 6:
Test Application
Session 7:
Test Generation
Session 8:
Concurrent Error Detection
- Cecilia Metra, Stefano Di Francescantonio, Giuseppe Marrale:
On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits.
207-215
Electronic Edition (IEEE Computer Society DL) BibTeX
- Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling.
216-224
Electronic Edition (IEEE Computer Society DL) BibTeX
- Francisco Rodríguez, José Carlos Campelo, Juan José Serrano:
A Memory Overhead valuation of the Interleaved Signature Instruction Stream.
225-232
Electronic Edition (IEEE Computer Society DL) BibTeX
- Fabio Salice, Mariagiovanna Sami, Renato Stefanelli:
Fault-Tolerant CAM Architectures: A Design Framework.
233-244
Electronic Edition (IEEE Computer Society DL) BibTeX
Session 9:
Fault Simulation and Injection II
Session 10:
Interconnect
Session 11:
Yield II
- Yuichi Hamamura, Kazunori Nemoto, Takaaki Kumazawa, Hisafumi Iwata, Kousuke Okuyama, Shiro Kamohara, Aritoshi Sugimoto:
Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure.
305-313
Electronic Edition (IEEE Computer Society DL) BibTeX
- Bing Qiu, Yvon Savaria, Meng Lu, Chunyan Wang, Claude Thibeault:
Yield Modeling of a WSI Telecom Router Architecture.
314-324
Electronic Edition (IEEE Computer Society DL) BibTeX
Session 12:
System-on-Chip Test
Session 13:
Feasibility of CED
Session 14:
Test
- A. Castelnuovo, Alessandro Fin, Franco Fummi, F. Sforza:
Emulation-Based Design Errors Identification.
365-371
Electronic Edition (IEEE Computer Society DL) BibTeX
- Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
A New Functional Fault Model for FPGA Application-Oriented Testing.
372-380
Electronic Edition (IEEE Computer Society DL) BibTeX
- Sagar S. Sabade, D. M. H. Walker:
Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis.
381-389
Electronic Edition (IEEE Computer Society DL) BibTeX
- Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz:
CMOS Standard Cells Characterization for IDDQ Testing.
390-398
Electronic Edition (IEEE Computer Society DL) BibTeX
- Tian Xia, Jien-Chung Lo:
On-Chip Jitter Measurement for Phase Locked Loops.
399-407
Electronic Edition (IEEE Computer Society DL) BibTeX
- Viera Stopjaková, D. Micusík, Lubica Benusková, Martin Margala:
Neural Networks-Based Parametric Testing of Analog IC.
408-418
Electronic Edition (IEEE Computer Society DL) BibTeX
Session 15:
Reliable and Repairable Memories
Copyright © Sat May 16 23:06:35 2009
by Michael Ley (ley@uni-trier.de)
