DFT 1998:
Austin,
TX,
USA
13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings.
IEEE Computer Society 1998, ISBN 0-8186-8832-7 BibTeX
@proceedings{DBLP:conf/dft/1998,
title = {13th International Symposium on Defect and Fault-Tolerance in
VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings},
booktitle = {DFT},
publisher = {IEEE Computer Society},
year = {1998},
isbn = {0-8186-8832-7},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Session 1:
Yield and Defect Density
Session 2:
Layout and Critical Area
Session 3:
Reliability Enhancement
Session 4:
Defect and Fault Analysis
- Dhamin Al-Khalili, Saman Adham, Come Rozon, Moazzem Hossain, D. Racz:
Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits.
84-92
Electronic Edition (IEEE Computer Society DL) BibTeX
- James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan:
Characterization of CMOS Defects using Transient Signal Analysis.
93-101
Electronic Edition (IEEE Computer Society DL) BibTeX
- Vijay R. Sar-Dessai, D. M. H. Walker:
Accurate Fault Modeling and Fault Simulation of Resistive Bridges.
102-107
Electronic Edition (IEEE Computer Society DL) BibTeX
- Xiao Sun, Carmie Hull:
Functional Verification Coverage vs. Physical Stuck-at Fault Coverage.
108-116
Electronic Edition (IEEE Computer Society DL) BibTeX
- Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda, Pierluigi Civera:
An Integrated HW and SW Fault Injection Environment for Real-Time Systems.
117-
Electronic Edition (IEEE Computer Society DL) BibTeX
Session 5:
Testing Techniques
Session 6:
Testing of Regular Structures
Session 7:
Concurrent Testing Techniques
Session 8:
Fault Diagnosis
Session 9:
Fault-Tolerant Designs I
Session 10:
Fault-Tolerant Designs II
Session 11:
High-Level Synthesis of Reliable Systems
Session 12:
Yield and Reliability Issues of Analog and Mixed Signal Circuits
Copyright © Sat May 16 23:06:35 2009
by Michael Ley (ley@uni-trier.de)
