6. SASP 2008: Anaheim, California, USA

Proceedings of the IEEE Symposium on Application Specific Processors, SASP 2008, held in conjunction with the DAC 2008, June 8-9, 2008, Anaheim, California, USA. IEEE 2008 BibTeX

High Level Synthesis and Custom Instructions

Jelena Trajkovic, Daniel D. Gajski:
Custom Processor Core Construction from C Code. 1-6
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Marcela Zuluaga, Nigel P. Topham:
Resource Sharing in Custom Instruction Set Extensions. 7-13
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Kenshu Seto, Masahiro Fujita:
Custom Instruction Generation with High-Level Synthesis. 14-19
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Alexandros Papakonstantinou, Deming Chen, Wen-mei W. Hwu:
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor. 20-25
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Reconfigurable Computing

Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi:
Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays. 26-33
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Carlos Morra, João M. P. Cardoso, João Bispo, Jürgen Becker:
Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures. 34-41
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Ali Irturk, Bridget Benson, Shahnam Mirzaei, Ryan Kastner:
An FPGA Design Space Exploration Tool for Matrix Inversion Architectures. 42-47
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Breakthrough Issues in Application Specific Processing

Sacha Loitz, Markus Wedler, Christian Brehm, Timo Vogt, Norbert Wehn, Wolfgang Kunz:
Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking. 48-54
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Bharat Sukhwani, Alessandro Forin, Richard Neil Pittman:
Extensible On-Chip Peripherals. 55-62
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Hai Lin, Guangyu Sun, Yunsi Fei, Yuan Xie, Anand Sivasubramaniam:
Thermal-aware Design Considerations for Application-Specific Instruction Set Processor. 63-68
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Kwangyoon Lee, Alex Orailoglu:
Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded Systems. 69-74
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Multiprocessing

Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria:
An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints. 75-82
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Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato:
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. 83-88
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Enric Musoll:
Energy and thermal tradeoffs in hardware-based load balancing for clustered multi-core architectures implementing power gating. 89-94
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Po-Kuan Huang, Matin Hashemi, Soheil Ghiasi:
System-Level Performance Estimation for Application-Specific MPSoC Interconnect Synthesis. 95-100
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Applications

Shuai Che, Jie Li, Jeremy W. Sheaffer, Kevin Skadron, John Lach:
Accelerating Compute-Intensive Applications with GPUs and FPGAs. 101-107
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Josef B. Spjut, Solomon Boulos, Daniel Kopta, Erik Brunvand, Spencer Kellis:
TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing. 108-114
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Wei Han, Ying Yi, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet T. Edorgan:
Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WiMAX Physical Layer. 115-120
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Xingdong Dai, Meghanad D. Wagh:
An MDCT Hardware Accelerator for MP3 Audio. 121-125
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