ISSS 2002:
Kyoto,
Japan
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan.
IEEE Computer Society 2002 BibTeX
@proceedings{DBLP:conf/isss/2002,
title = {Proceedings of the 15th International Symposium on System Synthesis
(ISSS 2002), October 2-4, 2002, Kyoto, Japan},
booktitle = {ISSS},
publisher = {IEEE Computer Society},
year = {2002},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Processor-Based System
- M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha:
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.
2-7
Electronic Edition (link) BibTeX
- Frank Vahid, Susan Cotterell:
Tuning of Loop Cache Architectures to Programs in Embedded System Design.
8-13
Electronic Edition (link) BibTeX
- Nader Bagherzadeh, Pai H. Chou, Jinfeng Liu:
Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors.
14-19
Electronic Edition (link) BibTeX
- Daniel Gajski, Junyu Peng:
Optimal Message-Passing for Data Coherency in Distributed Architecture.
20-25
Electronic Edition (link) BibTeX
- Ahmed Amine Jerraya, Damien Lyonnard, Samy Meftali, Frédéric Rousseau, Ferid Gharsalli:
Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design.
26-31
Electronic Edition (link) BibTeX
- Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin:
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems.
32-37
Electronic Edition (link) BibTeX
Reconfigurable System
Practical Experiences
- Andrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul:
System-Level Modeling of a Network Switch SoC.
62-67
Electronic Edition (link) BibTeX
- Erwin A. de Kock:
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study.
68-73
Electronic Edition (link) BibTeX
- Takao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto:
System-Level Design of IEEE1394 Bus Segment Bridge.
74-79
Electronic Edition (link) BibTeX
- Catherine H. Gebotys:
Security-Driven Exploration of Cryptography in DSP Cores.
80-85
Electronic Edition (link) BibTeX
- Ingo Sander, Axel Jantsch, Zhonghai Lu:
A Case Study of Hardware and Software Synthesis in ForSyDe.
86-91
Electronic Edition (link) BibTeX
Special Session on On-Chip Multi-Processing
Invited Talk
Design Methedologies Based on Instruction Code
- Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi:
A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design .
120-125
Electronic Edition (link) BibTeX
- Abhik Roychoudhury, Xianfeng Li, Tulika Mitra:
Timing Analysis of Embedded Software for Speculative Processors.
126-131
Electronic Edition (link) BibTeX
- William Fornaciari, Vito Trianni, Carlo Brandolese, Donatella Sciuto, Fabio Salice, Giovanni Beltrame:
Modeling Assembly Instruction Timing in Superscalar Architectures.
132-137
Electronic Edition (link) BibTeX
- Haris Lekatsas, Wayne Wolf, Yuan Xie:
Code Compression for VLIW Processors Using Variable-to-Fixed Coding.
138-143
Electronic Edition (link) BibTeX
- Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Qingfeng Zhuge:
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops.
144-149
Electronic Edition (link) BibTeX
Simulation and Verification
- Rainer Dömer, Andreas Gerstlauer, Wolfgang Mueller:
The Formal Execution Semantics of SpecC.
150-155
Electronic Edition (link) BibTeX
- Petru Eles, Zebo Peng, Daniel Karlsson:
Formal Verification in a Component-Based Reuse Methodology.
156-161
Electronic Edition (link) BibTeX
- Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima, Gabriela Nicolescu:
Validation in a Component-Based Design Flow for Multicore SoCs.
162-167
Electronic Edition (link) BibTeX
- Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu:
Efficient Simulation of Synthesis-Oriented System Level Designs.
168-173
Electronic Edition (link) BibTeX
- Soonhoi Ha, Sungchan Kim, Chan-Eun Rhee, Hyunguk Jung, Youngmin Yi, Dohyung Kim:
Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task Graphs.
174-179
Electronic Edition (link) BibTeX
- M. Balakrishnan, Anshul Kumar, C. P. Joshi:
A New Performance Evaluation Approach for System Level Design Space Exploration.
180-185
Electronic Edition (link) BibTeX
- Jürgen Ruf, Thomas Kropf, Jochen Klose:
A Visual Approach to Validating System Level Designs.
186-191
Electronic Edition (link) BibTeX
Special Session on Security on SoC
Low Power Memory System
- Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao:
Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems.
201-206
Electronic Edition (link) BibTeX
- Nikil D. Dutt, Daniel S. Hirschberg, Mahesh Mamidipaka:
Efficient Power Reduction Techniques for Time Multiplexed Address Buses.
207-212
Electronic Edition (link) BibTeX
- M. Balakrishnan, Peter Marwedel, Lars Wehmeyer, Nils Grunwald, Rajeshwari Banakar, Stefan Steinke:
Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory.
213-218
Electronic Edition (link) BibTeX
- Alex Orailoglu, Peter Petrov:
Low-Power Data Memory Communication for Application-Specific Embedded Processors.
219-224
Electronic Edition (link) BibTeX
- Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy:
System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory.
225-230
Electronic Edition (link) BibTeX
High Level and Architectural Synthesis
- Daniel Gajski, Andreas Gerstlauer:
System-Level Abstraction Semantics.
231-236
Electronic Edition (link) BibTeX
- Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer, Sergio Nocco, Claudio Passerone, Gianpiero Cabodi:
A Symbolic Approach for the Combined Solution of Scheduling and Allocation.
237-242
Electronic Edition (link) BibTeX
- Vincent John Mooney III, George F. Riley, Eung S. Shin:
Round-Robin Arbiter Design and Generation.
243-248
Electronic Edition (link) BibTeX
- Tsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya Kuwamura, Qiang Zhu:
An Object-Oriented Design Process for System-on-Chip Using UML.
249-254
Electronic Edition (link) BibTeX
- Juan Carlos López, Fernando Rincón, Francisco Moya, José Manuel Moya:
Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors.
255-260
Electronic Edition (link) BibTeX
- Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta:
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis.
261-266
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:26:25 2009
by Michael Ley (ley@uni-trier.de)
