ASAP 2008:
Leuven,
Belgium
19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008 Leuven, Belgium.
IEEE Computer Society 2008 BibTeX
Application-Specific Processor Instruction Sets
Interactive Session 1
- Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan:
Synthesis of application accelerators on Runtime Reconfigurable Hardware.
13-18
Electronic Edition (link) BibTeX
- Alexandru Amaricai, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan, Oana Boncalo:
Floating point multiplication rounding schemes for interval arithmetic.
19-24
Electronic Edition (link) BibTeX
- Sundar Balasubramanian, Harold W. Carter, Andrey Bogdanov, Andy Rupp, Jintai Ding:
Fast multivariate signature generation in hardware: The case of rainbow.
25-30
Electronic Edition (link) BibTeX
- Mohammad Hosseinabady, Jose Nunez-Yanez:
Fault-tolerant dynamically reconfigurable NoC-based SoC.
31-36
Electronic Edition (link) BibTeX
- Thomas Lorunser, Edwin Querasser, Thomas Matyus, Momtchil Peev, Johannes Wolkerstorfer, Michael Hutter, Alexander Szekely, Ilse Wimberger, Christian Pfaffel-Janser, Andreas Neppach:
Security processor with quantum key distribution.
37-42
Electronic Edition (link) BibTeX
- Pramod Kumar Meher, Jagdish Chandra Patra:
Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform.
43-48
Electronic Edition (link) BibTeX
- Ritesh Rajore, Ganesh Garga, H. S. Jamadagni, S. K. Nandy:
Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture.
49-54
Electronic Edition (link) BibTeX
- Tirath Ramdas, Gregory K. Egan, David Abramson, Kim Baldridge:
Run-time thread sorting to expose data-level parallelism.
55-60
Electronic Edition (link) BibTeX
System-level Interconnect and Mapping in SoCs
Advances in Cryptography
New Computational Methods
Novel Applications
New Directions in Application-Specific Design
Interactive Session 2
- Sherman Braganza, Miriam Leeser:
An efficient implementation of a phase unwrapping kernel on reconfigurable hardware.
138-143
Electronic Edition (link) BibTeX
- Holger Flatt, Steffen Blume, Sebastian Hesselbarth, Torsten Schünemann, Peter Pirsch:
A parallel hardware architecture for connected component labeling based on fast label merging.
144-149
Electronic Edition (link) BibTeX
- Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai:
Operation shuffling over cycle boundaries for low energy L0 clustering.
150-155
Electronic Edition (link) BibTeX
- Vamsi Kundeti, Yunsi Fei, Sanguthevar Rajasekaran:
An efficient digital circuit for implementing Sequence Alignment algorithm in an extended processor.
156-161
Electronic Edition (link) BibTeX
- Basant K. Mohanty, Pramod Kumar Meher:
Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform.
162-166
Electronic Edition (link) BibTeX
- Shahnam Mirzaei, Ali Irturk, Ryan Kastner, Brad T. Weals, Richard E. Cagley:
Design space exploration of a cooperative MIMO receiver for reconfigurable architectures.
167-172
Electronic Edition (link) BibTeX
- Mao Nakajima, Minoru Watanabe:
Dynamic holographic reconfiguration on a four-context ODRGA.
173-178
Electronic Edition (link) BibTeX
- Fernando Pardo, Paula López Martinez, Diego Cabello:
FPGA-based hardware accelerator of the heat equation with applications on infrared thermography.
179-184
Electronic Edition (link) BibTeX
- Masih Rahmaty, Mohammad S. Sadri, Mehdi Ataei Naeini:
FPGA based singular value decomposition for image processing applications.
185-190
Electronic Edition (link) BibTeX
Acceleration of Scientific and DSP Applications
- Arpith C. Jacob, Jeremy Buhler, Roger D. Chamberlain:
Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs.
191-196
Electronic Edition (link) BibTeX
- Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary F. Margrave:
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator.
197-202
Electronic Edition (link) BibTeX
- Ka Fai Cedric Yiu, Chun Hok Ho, Nedelko Grbic, Yao Lu, Xiaoxiang Shi, Wayne Luk:
Reconfigurable acceleration of microphone array algorithms for speech enhancement.
203-208
Electronic Edition (link) BibTeX
Advanced Communications Applications
Arithmetic
Interconnect and Mapping
- Andres Garcia, Mladen Berekovic, Tom Vander Aa:
Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor.
245-250
Electronic Edition (link) BibTeX
- Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan:
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router.
251-256
Electronic Edition (link) BibTeX
- Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre:
Loop-oriented metrics for exploring an application-specific architecture design-space.
257-262
Electronic Edition (link) BibTeX
Novel Processor and Memory System Techniques
Image and Video Processing
Copyright © Sat May 16 22:58:32 2009
by Michael Ley (ley@uni-trier.de)
