VLSI 1993: Grenoble, France

@proceedings{DBLP:conf/vlsi/1993,
  editor    = {Kakayuki Yanagawa and
               Peter A. Ivey},
  title     = {VLSI 93, Proceedings of the IFIP TC10/WG 10.5 International Conference
               on Very Large Scale Integration, Grenoble, France, 7-10 September,
               1993},
  booktitle = {VLSI},
  publisher = {North-Holland},
  series    = {IFIP Transactions},
  volume    = {A-42},
  year      = {1994},
  isbn      = {0-444-89911-1},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Keynote

• Joseph Borel, J. Monnier, G. Matheron: The single chip system era. 3-12 BibTeX

Layout Synthesis

• Daniel R. Brasen, Arnold Ginetti: Post-placement technology mapping. 15-24 BibTeX
• Yuji Shigehiro, Takashi Nagata, Isao Shirakawa, Takashi Kambe: Optimal layout recycling based on graph theoretic linear programming approach. 25-34 BibTeX
• Kim-Minh Nguyen, Martin C. Lefebvre: A family of module generators for the layout synthesis of I/O buffers. 35-44 BibTeX
• Lorenz Ladage, Georg Lodde: A 45° compaction algorithm handling overconstraints. 45-54 BibTeX

Special Purpose Architectures

• Hermann Hauser: Personal Communicators: A better way to stay in touch. 57-61 BibTeX
• Imed Moussa, Ali Skaf, Alain Guyot: Design of a GaAs redundant divider. 63-72 BibTeX
• Poul Martin Rands Jensen: An ASIC array architecture for the DITPOS algorithm. 73-82 BibTeX
• J. Morris Chang, Edward F. Gehringer: Performance of object caching for object-oriented systems. 83-91 BibTeX
• Ali Skaf, Jean-Claude Bajard, Alain Guyot, Jean-Michel Muller: A VLSI circuit for on-line polynominal computing: Application to exponential, trigonometric and hyperbolic functions. 93-100 BibTeX

Design for Testability

• Michael Gössel, Egor S. Sogomonyan: Self-parity cominational circuits for self-testing, concurrent fault detection and parity scan design. 103-111 BibTeX
• Albrecht P. Stroele: Partitioning and hierarchical description of self-testable designs. 113-122 BibTeX
• Régis Leveugle: Test of single fault tolerant controllers in VLSI circuits. 123-132 BibTeX
• W. A. J. Waller, S. M. Aziz: A C-testable parallel multiplier using differential cascode voltage switch (DDVS) logic. 133-142 BibTeX

Image Processing

• D. Poussart: Opportunities for integrating early-vision computation algorithms and VLSI technology to the development of smart sensors. 145-150 BibTeX
• J. Schönfeld, Peter Pirsch: Single board image processing unit for vehicle guidance. 151-160 BibTeX
• Jaap Smit, Mark J. Bentum, Martin M. Samsom: Implementation of the volume rendering algorithm using a low-power design-style. 161-168 BibTeX
• D. Jacquet, Gabriele Saucier: Design of a dedicated neural network on silicon: application to optical character recognition. 169-178 BibTeX

High Performance Processors

• Mike Muller: ARM6: Processor design for high performance at low power. 181-189 BibTeX
• Albert van der Werf, Emile H. L. Aarts, E. W. Heijnen, Jef L. van Meerbergen, Wim F. J. Verhaegh, Paul E. R. Lippens: A new method for retiming multi-functional processing units. 191-200 BibTeX
• Ganesh Gopalakrishnan, Venkatesh Akella: A transformational approach to asynchronous high-level synthesis. 201-210 BibTeX
• Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, J. V. Woods: A micropipelined ARM. 211-220 BibTeX
• F. Poirier, Jean-Claude Heudin, M. Belleville, C. Jaffard: A high performance RISC microprocessor. 221-228 BibTeX

Low Level Models

• Wolfgang Röthig, Elmar U. K. Melcher, Michel Dana: Probabilistic power consumption estimation in digital circuits. 231-240 BibTeX
• Maximilian Erbar, Ingo Könenkamp, Ernst-Helmut Horneber: Solving the partial differential equations of transmission lines with wave digital filters. 241-250 BibTeX
• M. Schneider, Utz Wever, Qinghua Zheng: Parallel harmonic balance. 251-260 BibTeX
• Norbert Wehn, Manfred Glesner, C. Vielhauer: Estimating lower hardware bounds in high-level synthesis. 261-270 BibTeX

Multichip Modules

• Christer Svensson, Jiren Yuan: Ultra high speed CMOS design. 273-282 BibTeX
• Claus M. Habiger, Ian P. Jalowiecki: The implementation of a MCM associative string processor. 283-289 BibTeX
• Bertrand Cabon, T. V. Dinh, J. Chilo: Superconductive interconnections in multi-chip modules. 291-298 BibTeX

Routing

• Mikiko Sode Tanaka, Masaki Ishikawa: A multilayer channel router based on optimal multilayer net assignment. 301-310 BibTeX
• Kevin Bolding, Sen-Ching Cheung, Sung-Eun Choi, Carl Ebeling, Soha Hassoun, Ton Anh Ngo, Robert Wille: The chaos router chip: design and implementation of an adaptive router. 311-320 BibTeX
• Tianxiong Xue, Takashi Fujii, Ernest S. Kuh: A new performance-driven global routing algorithm for gate array. 321-330 BibTeX

Simulation

• Shen Lin, Ernest S. Kuh: Circuit simulation for large interconnected IC networks. 333-342 BibTeX
• M. Müller: Bondgraph execution as a new algorithm for circuit simulation. 343-352 BibTeX
• Avinash C. Palaniswamy, Philip A. Wilsey: Adaptive checkpoint intervals in an optimistically synchronised parallel digital system simulator. 353-362 BibTeX