SBCCI 2008:
Gramado,
Brazil
Marcelo Lubaszewski, Michel Renovell, Rajesh K. Gupta (Eds.):
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008.
ACM 2008, ISBN 978-1-60558-231-3 BibTeX
Tutorials
Keynote
Invited talks
Technical panel
Design for yield
- Yanming Jia, Yici Cai, Xianlong Hong:
Full-chip routing system for reducing Cu CMP & ECP variation.
10-15
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- Laurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean Michel Portal:
Metal filling impact on standard cells: definition of the metal fill corner concept.
16-21
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- André V. Fidalgo, Gustavo R. Alves, Manuel G. Gericota, Jose M. Martins Ferreira:
A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures.
22-27
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- André Borin Soares, Alexsandro Cristovão Bonatto, Altamiro Amadeu Susin:
A new march sequence to fit DDR SDRAM test in burst mode.
28-33
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- Eduardo Luis Rhod, Luigi Carro:
An efficient test and characterization approach for nanowire-based architectures.
34-39
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Architectural design and synthesis in embedded systems
- Abner Correa Barros, Victor Wanderley Costa Medeiros, Viviane Lucy Santos Souza, Paulo Sérgio Brandão Nascimento, Ângelo Mazer, João Paulo Barbosa, Bruno P. Neves, Ismael Santos, Manoel Eusebio de Lima:
Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA.
40-45
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- Giancarlo C. Heck, Roberto A. Hexsel:
The performance of pollution control victim cache for embedded systems.
46-51
Electronic Edition (ACM DL) BibTeX
- Wagner Vieira Silvério, Janaína Domingues Costa, João Leonardo Fragoso, Julio Leão Silva Jr.:
Low-area ASIC implementation for configurable coefficients FIR pulse shape filters of digital TV systems.
52-57
Electronic Edition (ACM DL) BibTeX
- Levent Aksoy, Ece Olcay Gunes:
An approximate algorithm for the multiple constant multiplications problem.
58-63
Electronic Edition (ACM DL) BibTeX
- Levent Aksoy, Ece Olcay Gunes:
Area optimization algorithms in high-speed digital FIR filter synthesis.
64-69
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High performance circuits
- Rafaella Fiorelli, Fernando Silveira, Eduardo J. Peralías, Diego Vázquez, Adoración Rueda, José Luis Huertas:
A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM model.
70-75
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- Fernando da Rocha Paixão Cortes, Sergio Bampi:
A 40mhz 70db gain variable gain amplifier design using the gm/id design method.
76-80
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- Juan Mateus, Elkim Roa, Hugo Daniel Hernández, Wilhelmus A. M. Van Noije:
A 2.7ua sub1-v voltage reference.
81-84
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- Luciano Severino de Paula, Altamiro Amadeu Susin, Sergio Bampi:
A wide band CMOS differential voltage-controlled ring oscillator.
85-89
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- Marcio Barbosa Lucks, Nobuo Oki:
RBF circuits based on folded cascode differential pairs.
90-93
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Design for reliability
- Jader A. De Lima, Wallace A. Pimenta:
A current limiter for DC/DC regulators with internal compensation for process and temperature.
94-99
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- Pietro Maris Ferreira, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia:
Current mode read-out circuit for infrared photodiode applications in 0.35 mum cmos.
100-104
Electronic Edition (ACM DL) BibTeX
- Eduardo Conrad Jr., Fernando da Rocha Paixão Cortes, Sergio Bampi, Alessandro Girardi:
Early voltage and saturation voltage improvement in deep sub-micron technologies using associations of transistors.
105-110
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- Claas Cornelius, Frank Sill, Hagen Sämrow, Jakob Salzmann, Dirk Timmermann, Diógenes Cecilio da Silva Jr.:
Encountering gate oxide breakdown with shadow transistors to increase reliability.
111-116
Electronic Edition (ACM DL) BibTeX
Advances in low power design and power management
- Gustavo Wilke, Renan Fonseca, Cecilia Mezzomo, Ricardo Reis:
A novel scheme to reduce short-circuit power in mesh-based clock architectures.
117-122
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- Mahmoud Ben Naser, Csaba Andras Moritz:
Power and performance tradeoffs with process variation resilient adaptive cache architectures.
123-128
Electronic Edition (ACM DL) BibTeX
- Eduardo Ribeiro da Silva, Ivan Carlos Ribeiro do Nascimento, Frank Herman Behrens, Marcos Mauricio Pelicia, Remerson Stein Kickhofel, Ricardo Maltione:
Power management techniques for very low consumption and EMI reduction in automotive applications.
129-133
Electronic Edition (ACM DL) BibTeX
- Gustavo Rau de Almeida Callou, Paulo Romero Martins Maciel, Ermeson Carneiro de Andrade, Bruno Costa e Silva Nogueira, Eduardo Antonio Guimarães Tavares:
A coloured petri net based approach for estimating execution time and energy consumption in embedded systems.
134-139
Electronic Edition (ACM DL) BibTeX
- Felipe Ghellar, Marcelo Lubaszewski:
A novel AES cryptographic core highly resistant to differential power analysis attacks.
140-145
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Circuit optmization methods and tools
Networks-on-chip design and optimization
- Luciano Ost, Fernando Gehm Moraes, Leandro Möller, Leandro Soares Indrusiak, Manfred Glesner, Sanna Määttä, Jari Nurmi:
A simplified executable model to evaluate latency and throughput of networks-on-chip.
170-175
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- Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz:
Executable formal specification and validation of NoC communication infrastructures.
176-181
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- Fernando Gehm Moraes, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans:
MOTIM: an industrial application using nocs.
182-187
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FPGA and fault tolerant designs
- Helano Castro, Alexandre Augusto Coelho, Ricardo Jardel Silveira:
Fault-tolerance in FPGA's through CRC voting.
188-192
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- Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert:
Evaluating the robustness of secure triple track logic through prototyping.
193-198
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- Conrado Pilotto, José Rodrigo Azambuja, Fernanda Lima Kastensmidt:
Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications.
199-204
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- Andre Vilas Boas, Eduardo Ribeiro, Alfredo Olmos, Ricardo Maltione:
Self-adaptable slew rate control output buffer for embedded microcontroller port applications.
205-209
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- Julien Lallet, Sébastien Pillement, Olivier Sentieys:
Efficient dynamic reconfiguration for multi-context embedded FPGA.
210-215
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Advances in image compression architectures
- Marcelo Schiavon Porto, Sergio Bampi, Altamiro Amadeu Susin, Luciano Volcan Agostini:
Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV.
216-221
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- Ronaldo Husemann, Altamiro Amadeu Susin, Valter Roesler:
A new pipelined architecture of an H.264/MPEG-4 AVC deblocking filter.
222-227
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- Bruno Zatt, Altamiro Amadeu Susin, Sergio Bampi, Luciano Volcan Agostini:
High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV.
228-232
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- Hugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia:
Analog hardware implementation of a vector quantizer for focal-plane image compression.
233-238
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- Dieison Antonello Deprá, Vagner Santos Da Rosa, Sergio Bampi:
A novel hardware architecture design for binary arithmetic decoder engines based on bitstream flow analysis.
239-244
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Copyright © Sat May 16 23:36:49 2009
by Michael Ley (ley@uni-trier.de)
