ASAP 2005:
Samos,
Greece
16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece.
IEEE Computer Society 2005, ISBN 0-7695-2407-9 BibTeX
Cover Pages
Introduction
Keynote
Session 1:
Codesign Specification and Synthesis
- Thomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich:
Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems.
9-14
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- Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere:
Expression Synthesis in Process Networks generated by LAURA.
15-21
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- Bharath N, Nagaraju Bussa:
Artificial Deadlock Detection in Process Networks for ECLIPSE.
22-27
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- Alain Darte, Steven Derrien, Tanguy Risset:
Hardware/Software Interface for Multi-Dimensional Processor Arrays.
28-35
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- Kiyofumi Tanaka:
Casablanca II: Implementation of a Real-Time RISC.
36-42
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- Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere:
Behavioral specification of control interface for signal processing applications.
43-49
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- Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis:
Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware.
50-59
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- Karim Ben Chehida, Michel Auguin:
A SW/Configware Codesign Methodology for Control Dominated Applications.
56-64
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Session 2:
(Special) System Level Soc Design
Session 3:
Applications
Session 4:
Architectures,
ISA & Microarchitecture
- Ludovic L'Hours:
Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications.
127-133
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- Moboluwaji O. Sanu, Earl E. Swartzlander Jr.:
Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields.
134-139
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- Nikolaos Kavvadias, Spiridon Nikolaidis:
Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding.
140-145
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- Jan-Willem van de Waerdt, Stamatis Vassiliadis:
Instruction Set Architecture Enhancements for Video Processing.
146-153
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- Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers:
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.
154-160
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- Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis:
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays.
161-168
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- Byeong Kil Lee, Lizy Kurian John, Eugene John:
Architectural Support for Accelerating Congestion Control Applications in Network Processors.
169-178
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Session 5:
Power Aware Systems & VLSI CAD
- Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina:
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application.
179-184
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- Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou:
A Low-Power Processor Architecture Optimized forWireless Devices.
185-190
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- Vida Kianzad, Shuvra S. Bhattacharyya, Gang Qu:
CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded Systems.
191-197
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- Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan:
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield.
198-203
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- Thi Nguyen, Kaijian Shi:
Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs.
204-212
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Session 6:
(Special) Reconfigurable Computing
Session 7:
(Special) Nanocomputing
- Jie Han, Erin Taylor, Jianbo Gao, José A. B. Fortes:
Faults, Error Bounds and Reliability of Nanoelectronic Circuits.
247-253
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- Maria J. Avedillo, José M. Quintana, Héctor Pettenghi:
Logic Models Supporting the Design of MOBILE-based RTD Circuits.
254-259
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- Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, A. Rubio:
CONAN - A Design Exploration Framework for Reliable Nano-Electronics.
260-267
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- Bjørn Jager, Jörg-Christian Niemann, Ulrich Rückert:
Analytical approach to massively parallel architectures for nanotechnologies.
268-275
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- Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal:
On the Advantages of Serial Architectures for Low-Power Reliable Computations.
276-281
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- P. M. Kelly, T. Martin McGinnity, Liam P. Maguire:
Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems.
282-287
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- Konrad Walus, Mike Mazur, Gabriel Schulhof, Graham A. Jullien:
Simple 4-Bit Processor Based On Quantum-Dot Cellular Automata (QCA).
288-293
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- Cor Meenderinck, Sorin Cotofana, Casper Lageweg:
High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology.
294-302
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Session 8:
Arithmetic
Session 9:
Cryptography and Coding
- Hans Eberle, Arvinderpal Wander, Nils Gura, Sheueling Chang Shantz, Vipul Gupta:
Architectural Extensions for Elliptic Curve Cryptography over GF(2m) on 8-bit Microprocessors.
343-349
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- Lejla Batina, Nele Mentens, Bart Preneel, Ingrid Verbauwhede:
Side-channel aware design: Algorithms and Architectures for Elliptic Curve Cryptography over GF(2n).
350-355
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- A. Murat Fiskiran, Ruby B. Lee:
On-Chip Lookup Tables for Fast Symmetric-Key Encryption.
356-363
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- Suman Mamidi, Daniel Iancu, Andrei Iancu, Michael J. Schulte, John Glossner:
Instruction Set Extensions for Reed-Solomon Encoding and Decoding.
364-369
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- Perttu Salmela, Tuomas Järvinen, Teemu Sipilä, Jarmo Takala:
256-State Rate 1/2 Viterbi Decoder on TTA Processor.
370-378
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Session 10:
Signal and Video Processing
- M. Van Der Horst, Kees van Berkel, Johan Lukkien, Rudolf H. Mak:
Recursive Filtering on a Vector DSP with Linear Speedup.
379-386
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- Ian Steiner, P. Chan, Laurent Imbert, Graham A. Jullien, Vassil S. Dimitrov, G. H. McGibney:
A Fault-Tolerant Modulus Replication Complex FIR Filter.
387-392
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- Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis:
Performance Comparison of SIMD Implementations of the Discrete Wavelet Transform.
393-398
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- Michael T. Frederick, Nathan A. VanderHorn, Arun K. Somani:
Real-time H/W Implementation of the Approximate Discrete Radon Transform.
399-404
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- Tom R. Jacobs, José L. Núñez-Yáñez:
A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor.
405-410
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- José L. Núñez-Yáñez, Vassilios A. Chouliaras:
Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec.
411-416
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Copyright © Sat May 16 22:58:33 2009
by Michael Ley (ley@uni-trier.de)
