27. HICSS 1994:
Maui,
Hawaii,
USA - Volume 1
27th Annual Hawaii International Conference on System Sciences (HICSS-27),
January 4-7,
1994,
Maui,
Hawaii. IEEE Computer Society,
1994,
Volume 1:
Architecture,
ISBN 0-8186-5050-8
Computer Design:
A New Grand Challenge
Design and Prototyping of Digital Signal Processing (DSP) Systems
- Jordi Cortadella, José A. B. Fortes, Edward A. Lee:
Design and Prototyping of Digital Signal Processing (DSP) Systems: Introduction.
56-57 BibTeX
- Wayne Burleson:
Using Regular Array Methods for DSP Module Synthesis.
58-67 BibTeX
- Guoning Liao, Erik R. Altman, Vinod K. Agarwal, Guang R. Gao:
A Comparative Study of Multiprocessor List Scheduling Heuristics.
68-77 BibTeX
- Hans-Jürgen Herpel, Michael Held, Manfred Glesner:
A Design Methodology for the Conceptual Design of Application Specific Digital Processors in Mechatronic Systems.
78-86 BibTeX
- William Cammack, Mark Paley:
Fixpt: A C++ Method for Development of Fixed Point Digital Signal Processing Algorithms.
87-95 BibTeX
- Manjit Borah, Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
The MGAP: A High Performance, User Programmable, Multifunctional Architecture for DS.
96-104 BibTeX
- Joël Champeau, Luc Le Pape, Bernard Pottier, Stéphane Rubini, Eric Gautrin, Laurent Perraudeau:
Flexible Parallel FPGA-Based Architectures with ArMe.
105-113 BibTeX
- Vijay K. Jain, Hiroomi Hikawa:
Parallel Architecture for Universal Digital Signal Processing.
114-123 BibTeX
- Catherine H. Gebotys, Robert J. Gebotys:
Application-Specific Architectures for Field-Programmable VLSI Technologies.
124-131 BibTeX
Enabling Multiprocessor Technology
- Wen-Hann Wang, Shreekant S. Thakkar:
Enabling Multiprocessor Technology: Introduction.
132-133 BibTeX
- Mike Galles, Eric Williams:
Performance Optimizations, Implementation, and Verification of the SGI Challenge Multiprocessor.
134-143 BibTeX
- Andreas Nowatzyk, Gunes Aybay, Michael C. Browne, Edmund J. Kelly, David Lee, Michael Parkin:
The S3mp Scalable Shared Memory Multiprocessor.
144-153 BibTeX
- Stein Gjessing, Glen Stone:
Performance of the RamLink Memory Architecture.
154-162 BibTeX
- Richard N. Zucker, Jean-Loup Baer:
Software versus Hardware Coherence: Performance versus Cos.
163-172 BibTeX
- Ziqiang Liu, José Duato:
Adaptive Unicast and Multicast in 3D Mesh Networks.
173-183 BibTeX
Fast Simulation of Computer Architectures
- Thomas M. Conte, Charles E. Gimarc:
Fast Simulation of Computer Architectures: Introduction.
184 BibTeX
- H. A. Rizvi, James B. Sinclair, J. Robert Jump, J. Carson:
Execution-Driven Simulation of a Superscalar Processor.
185-194 BibTeX
- Wayne Yamamoto, Mauricio J. Serrano, Adam R. Talcott, Roger C. Wood, Mario Nemirovsky:
Performance Estimation of Multistreamed, Supersealar Processors.
195-204 BibTeX
- Gary Lauterbach:
Accelerating Architectural Simulation by Parallel Execution of Trace Samples.
205-210 BibTeX
- John W. C. Fu, Janak H. Patel:
Trace Driven Simulation using Sampled Traces.
211-220 BibTeX
- Si-En Chang, Chia-Chang Hsu:
Efficient Simulation Methods for Multi-Level Cache Memory Hierarchies.
221-230 BibTeX
- Santosh G. Abraham, Rabin A. Sugumar:
Fast Efficient Simulation of Write-Buffer Configurations.
231-240 BibTeX
- Gudjon Hermannsson, Ai Li, Larry D. Wittie:
EC/DSIM: A Frontend and Simulator for Huge Parallel Systems.
241-250 BibTeX
- Bob Boothe:
Fast Accurate Simulation of Large Shared Memory Multiprocessors.
251-260 BibTeX
- Alexander R. Robertson, Roland N. Ibbett:
HASE: A Flexible High Performance Architecture Simulator.
261-270 BibTeX
- Sathiamoorthy Manoharan, Nigel P. Topham, A. W. R. Crawford:
Trace-Driven Simulation of Decoupled Architectures.
271-279 BibTeX
High-Performance Computer Arithmetic and Implementations
- Vojin G. Oklobdzija:
High-Performance Computer Arithmetic and Implementations: Introduction.
280-281 BibTeX
- Yousuke Ohno, Junichiro Makino, Izumi Hachisu, Toshikazu Ebisuzaki, Daiichiro Sugimoto:
DREAM-1A: Special-Purpose Computer for Computational Fluid Dynamics.
282-291 BibTeX
- Eiichiro Kokubo, Junichiro Makino, Makoto Taiji:
HARP-1: A Special-Purpose Computer for itN-body Simulation with the Hermite Integrator.
292-301 BibTeX
- Makino Taiji, Junichiro Makino, Eiichiro Kokubo, Toshikazu Ebisuzaki, Daiichiro Sugimoto:
HARP Chip: A.600 Mflops Application-Specific LSI for Astrophysical itN-body Simulations.
302-311 BibTeX
- Andrej Skorc, Veljko M. Milutinovic:
Architectural Requirements for Multimedia Image Compression, and a Solution Based on VLSI Hardware Accelerator.
312-320 BibTeX
- Alberto Broggi:
Speeding-up Mathematical Morphology Computations with Special-Purpose Array Processors.
321-330 BibTeX
- Paolo Montuschi, Luigi Ciminiera:
Radix-2 Division with Quotient Digit Prediction without Prescaling.
331-338 BibTeX
- Jack Bukkoldt Andersen, Anders Færgemand Nielsen, Ole Olsen:
A Systolic ON-LINE Non-Restoring Division Scheme.
339-348 BibTeX
- Weng-Fai Wong, Eiichi Goto:
Fast Evaluation of the Elementary Functions in Double Precision.
349-359 BibTeX
High-Performance Implementation Techniques of Superscalar,
VLIW,
Deeply Pipelined,
Multi-Threaded,
Vector,
and Dataglow Execution Architectures
- Pohua P. Chang:
Introduction.
360 BibTeX
- Pradeep K. Dubey, Arvind Krishna, Michael J. Flynn:
Analytical Modeling of Multithreaded Pipeline Performance.
361-367 BibTeX
- Hiroshi Nakamura, Kisaburo Nakazawa, Hang Li, Hiromitsu Imori, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita:
Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers.
368-377 BibTeX
- Phenil Patadia, Vijay Karani, Krishna M. Kavi, Ponnarasu Shanmugam, Behrooz Shirazi, Ali R. Hurson:
Improvements to the ETS Dynamic Dataflow Architecture.
378-387 BibTeX
- Feipei Lai, Fong-chou Tsai:
A Pipeline Bubbles Reduction Technique for the Monsoon Dataflow Architecture.
388-397 BibTeX
- Takaya Arita, Hiromitsu Takagi, Masahiro Sowa:
V++: An Instruction-Restructurable Processor Architecture.
398-408 BibTeX
Memory Organization Tradeoffs in Computer Systems Design
- John W. C. Fu, A. L. Narasimha Reddy:
Introduction.
409-411 BibTeX
- Dimitrios Stiliadis, Anujan Varma:
Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches.
412-421 BibTeX
- Ju-Ho Tang, Kimming So:
Performance and Design Choices of Level-Two Caches.
422-430 BibTeX
- Sally A. McKee, Robert H. Klenke, Andrew J. Schwab, William A. Wulf, Steven A. Moyer, James H. Aylor, Charles Y. Hitchcock:
Experimental Implementation of Dynamic Access Ordering.
431-440 BibTeX
- Arnold J. Niessen, Harry A. G. Wijshoff:
Memory Hardware Support for Sparse Computations.
441-450 BibTeX
- Brian Marsh, Fred Douglis, P. Krishnan:
Flash Memory File Caching for Mobile Computers.
451-461 BibTeX
Photonics and Electronics in Computer System Design
- Aruna V. Ramanan, Harry F. Jordan, Jon R. Sauer, Daniel J. Blumenthal:
An Extended Fiber-Optic Backplane for Multiprocessors.
462-470 BibTeX
- Francis Reichmeyer, Salim Hariri, Wang Song, Kamal Jabbour:
An Optical Hypercube Local Area Network.
471-480 BibTeX
- Pawel Gburzynski, Jacek Maitan, D. Robertson:
A Simple and Scalable Architecture for Rapidly Expandable Networks.
481-490 BibTeX
- Aloke Guha:
Optical Packet Switching Architectures for Distributed Computing.
491-498 BibTeX
- Michael S. Borella, Biswanath Mukherjee, Feiling Jia, S. Ramamurthy, Dhritiman Banerjee, Jason Iness:
Optical Interconnects for Multiprocessor Architectures Using Wavelength-Division Multiplexing.
499-508 BibTeX
- Paul R. Prucnal:
Time-Division Optical Micro-Area Networks.
509-519 BibTeX
Scalable Shared-Memory Architectures
Copyright © Sat May 16 23:14:27 2009
by Michael Ley (ley@uni-trier.de)
