11. RSP 2000:
Paris,
France
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000),
21-23 June 2000,
Paris,
France. IEEE Computer Society,
online publication:
http://computer.org/proceedings/rsp/0668/0668toc.htm
Session 1:
Co-Design Methodologies
Session 2:
Software Methodologies
Session 3:
Tools
Session 4:
Real Time Systems
Session 5:
Hardware Methodologies
Session 6:
Code Generation
Session 7:
Methodologies
Session 8:
Reconfigurability in Hardware Systems
Session 9:
Hardware Systems
- Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu:
Power-Constrained Block-Test List Scheduling.
182-187
Electronic Edition (IEEE Computer Society DL) BibTeX
- Juan de Vicente, Juan Lanchares, Román Hermida:
Adaptive FPGA Placement by Natural Optimization.
188-193
Electronic Edition (IEEE Computer Society DL) BibTeX
- Yajun Ha, Patrick Schaumont, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man:
A Hardware Virtual Machine for the Networked Reconfiguration.
194-199
Electronic Edition (IEEE Computer Society DL) BibTeX
- Helena Krupnova, Gabriele Saucier:
FPGA Technology Snapshot: Current Devices and Design Tools.
200-
Electronic Edition (IEEE Computer Society DL) BibTeX
Session 10:
Industrial Session
Session 11:
Methodologies
Session 12:
Embedded Systems
Copyright © Sat May 16 23:36:05 2009
by Michael Ley (ley@uni-trier.de)