| 2008 |
|---|
| 6 | EE | Leandro Soares Indrusiak,
Luciano Ost,
Leandro Möller,
Fernando Moraes,
Manfred Glesner:
Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects.
ISVLSI 2008: 491-494 |
| 5 | EE | Luciano Ost,
Fernando Gehm Moraes,
Leandro Möller,
Leandro Soares Indrusiak,
Manfred Glesner,
Sanna Määttä,
Jari Nurmi:
A simplified executable model to evaluate latency and throughput of networks-on-chip.
SBCCI 2008: 170-175 |
| 2006 |
|---|
| 4 | EE | Melissa Vetromille,
Luciano Ost,
César A. M. Marcon,
Carlos Eduardo Reif,
Fabiano Hessel:
RTOS Scheduler Implementation in Hardware and Software for Real Time Applications.
IEEE International Workshop on Rapid System Prototyping 2006: 163-168 |
| 2005 |
|---|
| 3 | EE | Luciano Ost,
Aline Mello,
José Palma,
Fernando Gehm Moraes,
Ney Calazans:
MAIA: a framework for networks on chip generation and verification.
ASP-DAC 2005: 49-52 |
| 2004 |
|---|
| 2 | EE | Fernando Gehm Moraes,
Ney Calazans,
Aline Mello,
Leandro Möller,
Luciano Ost:
HERMES: an infrastructure for low area overhead packet-switching networks on chip.
Integration 38(1): 69-93 (2004) |
| 2003 |
|---|
| 1 | | Fernando Gehm Moraes,
Aline Mello,
Leandro Möller,
Luciano Ost,
Ney Laert Vilar Calazans:
A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping.
VLSI-SOC 2003: 318-323 |
