| 2004 |
|---|
| 11 | EE | S. Crossley,
N. Luke Seed,
Neil A. Thacker,
Peter A. Ivey:
Improving accuracy, robustness and computational efficiency in 3D computer vision.
Image Vision Comput. 22(5): 399-412 (2004) |
| 2002 |
|---|
| 10 | EE | Mehdi Mahdavi,
R. M. Edwards,
C. Ladas,
Peter A. Ivey:
Analytic performance of a random access protocol with mixed services of voice and a finite number of data sessions in mobile cellular networks.
MWCN 2002: 327-331 |
| 9 | | A. C. Zawada,
N. Luke Seed,
Peter A. Ivey:
Continuous and high coverage self-testing of dynamically re-configurable systems.
Parallel Computing 28(7-8): 1155-1178 (2002) |
| 1999 |
|---|
| 8 | | Mihai Munteanu,
Peter A. Ivey,
N. Luke Seed,
Marios Psilogeorgopoulos,
Neil Powell,
Istvan Bogdan:
Single Ended Pass-Transistor Logic - A Comparison with CMOS and CPL.
VLSI 1999: 206-218 |
| 1996 |
|---|
| 7 | EE | Steven P. Larcombe,
David J. Prendergast,
Neil A. Thacker,
Peter A. Ivey:
Using Genetic Algorithms to Automate System Implementation in a Novel Three-Dimensional Packaging Technolog.
ICCD 1996: 274-279 |
| 6 | EE | Richard A. Lane,
Neil A. Thacker,
N. Luke Seed,
Peter A. Ivey:
A Generalized Computer Vision Chip.
Real-Time Imaging 2(4): 203-213 (1996) |
| 1994 |
|---|
| 5 | | Kakayuki Yanagawa,
Peter A. Ivey:
VLSI 93, Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration, Grenoble, France, 7-10 September, 1993
North-Holland 1994 |
| 4 | | Jason L. Kelly,
Peter A. Ivey:
Defect Tolerant SRAM Based FPGAs.
ICCD 1994: 479-482 |
| 3 | | Rob Yates,
Stephen Evans,
Peter A. Ivey:
A 1.2 Billion Operations per Second Video Signal Processing Chip.
ICIP (3) 1994: 596-600 |
| 2 | | J. Goodenough,
R. J. Meacham,
J. D. Morris,
N. Luke Seed,
Peter A. Ivey:
A General Purpose, Single Chip Video Signal Processing (VSP) Architecture for Image Processing, Coding and Computer Vision.
ICIP (3) 1994: 601-605 |
| 1988 |
|---|
| 1 | | Manfred Glesner,
M. Huch,
Peter A. Ivey,
T. Midwinter,
Gabriele Saucier,
Jacques Trilhe:
Entwurf eines systolischen Arrays in Wafer Scale Technik für die digitale Signalverarbeitung.
GI Jahrestagung (2) 1988: 75-91 |
