11. FPL 2001:
Belfast,
Northern Ireland,
UK
Gordon J. Brebner, Roger Woods (Eds.):
Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings.
Lecture Notes in Computer Science 2147 Springer 2001, ISBN 3-540-42499-7 BibTeX
@proceedings{DBLP:conf/fpl/2001,
editor = {Gordon J. Brebner and
Roger Woods},
title = {Field-Programmable Logic and Applications, 11th International
Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29,
2001, Proceedings},
booktitle = {FPL},
publisher = {Springer},
series = {Lecture Notes in Computer Science},
volume = {2147},
year = {2001},
isbn = {3-540-42499-7},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Invited Keynote 1
Architectural Frameworks
- Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek:
Prototyping Framework for Reconfigurable Processors.
6-16
Electronic Edition (link) BibTeX
- Chris Fisher, Kevin Rennie, Guanbin Xing, Stefan G. Berg, Kevin Bolding, John H. Naegle, Daniel Parshall, Dmitriy Portnov, Adnan Sulejmanpasic, Carl Ebeling:
An Emulator for Exploring RaPiD Configurable Computing Architectures.
17-26
Electronic Edition (link) BibTeX
Place and Route 1
Architecture
DSP 1
- Stephen J. Melnikoff, Steven F. Quigley, Martin J. Russell:
Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic.
81-90
Electronic Edition (link) BibTeX
- Felix Albu, Jiri Kadlec, Christopher I. Softley, Rudolf Matousek, Antonin Hermanek, Nick Coleman, Anthony Fagan:
Implementation of (Normalised) RLS Lattice on Virtex.
91-100
Electronic Edition (link) BibTeX
- Abbes Amira, Ahmed Bouridane, Peter Milligan:
Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing.
101-111
Electronic Edition (link) BibTeX
Synthesis
Encryption
Runtime Reconfiguration 1
Graphics and Vision
Invited Keynote 2
Place and Route 2
Networking
Processor Interaction
Applications
Methodology 1
DSP 2
Loops and Systolic
Image Processing
Invited Keynote 3
Runtime Reconfiguration 2
Faults
Methodology 2
Arithmetic
Short Papers 1
- Jürgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred Glesner:
Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures.
584-589
Electronic Edition (link) BibTeX
- Cristian Ciressan, Eduardo Sanchez, Martin Rajman, Jean-Cédric Chappelier:
An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars.
590-594
Electronic Edition (link) BibTeX
- Jim Harkin, T. Martin McGinnity, Liam P. Maguire:
Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach.
595-600
Electronic Edition (link) BibTeX
- Tsutomu Maruyama, Yoshiki Yamaguchi, Atsushi Kawase:
An Approach to Real-Time Visualization of PIV Method with FPGA.
601-606
Electronic Edition (link) BibTeX
- Mokhtar Nibouche, Ahmed Bouridane, Fionn Murtagh, Omar Nibouche:
FPGA-Based Discrete Wavelet Transforms System.
607-612
Electronic Edition (link) BibTeX
- Jose Luis Nunez, Claudia Feregrino, Simon Jones, Stephen Bateman:
X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor.
613-617
Electronic Edition (link) BibTeX
- Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara:
Arithmetic Operation Oriented Reconfigurable Chip: RHW.
618-622
Electronic Edition (link) BibTeX
Short Papers 2
- Michael Dales:
Initial Analysis of the Proteus Architecture.
623-627
Electronic Edition (link) BibTeX
- Eric Keller:
Building Asynchronous Circuits with JBits.
628-632
Electronic Edition (link) BibTeX
- Thomas Lehmann, Andreas Schreckenberg:
Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux.
633-637
Electronic Edition (link) BibTeX
- Raymond Sinnappan, Scott Hazelhurst:
A Reconfigurable Approach to Packet Filtering.
638-642
Electronic Edition (link) BibTeX
- Riad Stefo, Jose Luis Nunez, Claudia Feregrino, Sudipta Mahapatra, Simon Jones:
FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding.
643-647
Electronic Edition (link) BibTeX
- Ram Subramanian, Santosh Pande:
A Data Re-use Based Compiler Optimization for FPGAs.
648-652
Electronic Edition (link) BibTeX
- Matti Tommiska, Jorma Skyttä:
Dijkstra's Shortest Path Routing Algorithm in Reconfigurable Hardware.
653-657
Electronic Edition (link) BibTeX
- Isidoro Urriza, José I. García-Nicolás, Alfredo Sanz, Antonio Valdovinos:
A System on Chip for Power Line Communications According to European Home Systems Specifications.
658-662
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:12:42 2009
by Michael Ley (ley@uni-trier.de)