Mrinal Bose

2009
5	EE	Di Wang, Vyas Venkataraman, Zhen Wang, Wei Qin, Hangsheng Wang, Mrinal Bose, Jayanta Bhadra: Accelerating multi-party scheduling for transaction-level modeling. ACM Great Lakes Symposium on VLSI 2009: 339-344
4	EE	Mrinal Bose, Prashant Naphade, Jayanta Bhadra, Hillel Miller: An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs. ISQED 2009: 377-381
2003
3	EE	Mrinal Bose, Mark H. Nodine, William R. Jurasz Jr., Vlad Zavadsky, Arvind Chodavadia, Lincoln R. Nunes: Modeling IP Responses in Testcase Generation for Systems-on-Chip Verification. MTV 2003: 7-10
2001
2	EE	Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir: Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. IOLTW 2001: 65-
1999
1	EE	Partha Pratim Chakrabarti, Pallab Dasgupta, Partha Pratim Das, Arnob Roy, Shuvendu K. Lahiri, Mrinal Bose: Controlling State Explosion in Static Simulation by Selective Composition. VLSI Design 1999: 226-231

Coauthor Index

1	Magdy S. Abadir	[2]
2	Jayanta Bhadra	[4] [5]
3	P. P. Chakrabarti (Partha Pratim Chakrabarti)	[1]
4	Arvind Chodavadia	[3]
5	Partha Pratim Das	[1]
6	Pallab Dasgupta	[1]
7	William R. Jurasz Jr.	[3]
8	Shuvendu K. Lahiri	[1]
9	Hillel Miller	[4]
10	Prashant Naphade	[4]
11	Mark H. Nodine	[3]
12	Lincoln R. Nunes	[3]
13	Wei Qin	[5]
14	Arnob Roy	[1]
15	Elizabeth M. Rudnick	[2]
16	Vyas Venkataraman	[5]
17	Di Wang	[5]
18	Hangsheng Wang	[5]
19	Zhen Wang	[5]
20	Vlad Zavadsky	[3]

Colors in the list of coauthors