| 2008 |
|---|
| 7 | EE | Brian Keng,
Hratch Mangassarian,
Andreas G. Veneris:
A succinct memory model for automated design debugging.
ICCAD 2008: 137-142 |
| 2007 |
|---|
| 6 | EE | Sean Safarpour,
Andreas G. Veneris,
Hratch Mangassarian:
Trace Compaction using SAT-based Reachability Analysis.
ASP-DAC 2007: 932-937 |
| 5 | EE | Hratch Mangassarian,
Andreas G. Veneris,
Sean Safarpour,
Farid N. Najm,
Magdy S. Abadir:
Maximum circuit activity estimation using pseudo-boolean satisfiability.
DATE 2007: 1538-1543 |
| 4 | EE | Sean Safarpour,
Hratch Mangassarian,
Andreas G. Veneris,
Mark H. Liffiton,
Karem A. Sakallah:
Improved Design Debugging Using Maximum Satisfiability.
FMCAD 2007: 13-19 |
| 3 | EE | Hratch Mangassarian,
Andreas G. Veneris,
Sean Safarpour,
Marco Benedetti,
Duncan Smith:
A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test.
ICCAD 2007: 240-245 |
| 2 | EE | Hratch Mangassarian,
Hassan Artail:
A general framework for subjective information extraction from unstructured English text.
Data Knowl. Eng. 62(2): 352-367 (2007) |
| 2005 |
|---|
| 1 | EE | Hratch Mangassarian,
Mohab Anis:
On Statistical Timing Analysis with Inter- and Intra-Die Variations.
DATE 2005: 132-137 |
