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Rajesh Garg

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2009
18EEKalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri: Low power and high performance sram design using bank-based selective forward body bias. ACM Great Lakes Symposium on VLSI 2009: 441-444
17EESuganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya: Design and implementation of a sub-threshold BFSK transmitter. ISQED 2009: 664-672
16EERajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi: SEU hardened clock regeneration circuits. ISQED 2009: 806-813
2008
15EEArunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri: A robust, fast pulsed flip-flop design. ACM Great Lakes Symposium on VLSI 2008: 119-122
14EESuganth Paul, Rajesh Garg, Sunil P. Khatri: Pipelined network of PLA based circuit design. ACM Great Lakes Symposium on VLSI 2008: 213-218
13EESalman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng: A lithography-friendly structured ASIC design approach. ACM Great Lakes Symposium on VLSI 2008: 315-320
12EERajesh Garg, Charu Nagpal, Sunil P. Khatri: A fast, analytical estimator for the SEU-induced pulse width in combinational designs. DAC 2008: 918-923
11EECharu Nagpal, Rajesh Garg, Sunil P. Khatri: A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. DATE 2008: 354-359
10EERajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri: A Single-supply True Voltage Level Shifter. DATE 2008: 979-984
9EERajesh Garg, Sunil P. Khatri: A novel, highly SEU tolerant digital circuit design approach. ICCD 2008: 14-20
8EERajesh Garg, Peng Li, Sunil P. Khatri: Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). ISCAS 2008: 1788-1791
2007
7EEJeff L. Cobb, Rajesh Garg, Sunil P. Khatri: A methodology for interconnect dimension determination. ISPD 2007: 189-195
2006
6EERajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri: A design flow to optimize circuit delay by using standard cells and PLAs. ACM Great Lakes Symposium on VLSI 2006: 217-222
5EENikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri: A PLA based asynchronous micropipelining approach for subthreshold circuit design. DAC 2006: 419-424
4EERajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi: A design approach for radiation-hard digital electronics. DAC 2006: 773-778
3EEEric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri: CMOS Comparators for High-Speed and Low-Power Applications. ICCD 2006
2EERajesh Garg, Nikhil Jayakumar, Sunil P. Khatri: On the Improvement of Statistical Static Timing Analysis. ICCD 2006
1EERajesh Garg, Sunil P. Khatri: Generalized buffering of PTL logic stages using Boolean division. ISCAS 2006

Coauthor Index

1Kalyana C. Bollapalli [18]
2Mosong Cheng [13]
3Gwan S. Choi (Gwan Choi) [4] [16]
4Jeff L. Cobb [7]
5Rajballav Dash [16]
6Bruce Gamache [5]
7Salman Gopalani [13]
8Kanupriya Gulati [6] [18]
9Anshul Gupta [6]
10Nikhil Jayakumar [2] [4] [5] [6]
11Sunil P. Khatri [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18]
12Peng Li [8]
13Dumezie Maduike [3]
14Gagandeep Mallarapu [10]
15Eric Menendez [3]
16Charu Nagpal [11] [12]
17Suganth Paul [14] [17]
18Mario Sanchez [6]
19Sheila Vaidya [17]
20Arunprasad Venkatraman [15]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)