| 2008 |
|---|
| 9 | EE | Noel Eisley,
Li-Shiuan Peh,
Li Shang:
Leveraging on-chip networks for data cache migration in chip multiprocessors.
PACT 2008: 197-207 |
| 2007 |
|---|
| 8 | EE | Vassos Soteriou,
Noel Eisley,
Hangsheng Wang,
Bin Li,
Li-Shiuan Peh:
Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks.
IEEE Trans. VLSI Syst. 15(8): 855-868 (2007) |
| 7 | EE | Vassos Soteriou,
Noel Eisley,
Li-Shiuan Peh:
Software-directed power-aware interconnection networks.
TACO 4(1): (2007) |
| 2006 |
|---|
| 6 | EE | Noel Eisley,
Vassos Soteriou,
Li-Shiuan Peh:
High-level power analysis for multi-core chips.
CASES 2006: 389-400 |
| 5 | EE | Vassos Soteriou,
Noel Eisley,
Hangsheng Wang,
Bin Li,
Li-Shiuan Peh:
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks.
ICCD 2006 |
| 4 | EE | Noel Eisley,
Li-Shiuan Peh,
Li Shang:
In-Network Cache Coherence.
MICRO 2006: 321-332 |
| 3 | EE | Noel Eisley,
Li-Shiuan Peh,
Li Shang:
In-network cache coherence.
Computer Architecture Letters 5(1): 34-37 (2006) |
| 2005 |
|---|
| 2 | EE | Vassos Soteriou,
Noel Eisley,
Li-Shiuan Peh:
Software-directed power-aware interconnection networks.
CASES 2005: 274-285 |
| 2004 |
|---|
| 1 | EE | Noel Eisley,
Li-Shiuan Peh:
High-level power analysis for on-chip networks.
CASES 2004: 104-115 |
