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Eric Rotenberg

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2009
34EEHashem Hashemi Najaf-abadi, Eric Rotenberg: Architectural Contesting. HPCA 2009: 189-200
2008
33EEVimal K. Reddy, Eric Rotenberg: Coverage of a microarchitecture-level fault check regimen in a superscalar processor. DSN 2008: 1-10
32EEHashem Hashemi Najaf-abadi, Eric Rotenberg: Configurational Workload Characterization. ISPASS 2008: 147-156
2007
31EEVimal K. Reddy, Eric Rotenberg: Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance. DSN 2007: 307-316
30EEAhmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary: Transparent control independence (TCI). ISCA 2007: 448-459
29EERavi K. Venkatesan, Ahmed S. Al-Zawawi, Krishnan Sivasubramanian, Eric Rotenberg: ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling. IEEE Trans. Computers 56(2): 147-160 (2007)
2006
28EEVimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy: Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance. ASPLOS 2006: 83-94
27EERavi K. Venkatesan, Stephen Herr, Eric Rotenberg: Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM. HPCA 2006: 155-165
26EEVimal K. Reddy, Eric Rotenberg, Ahmed S. Al-Zawawi: Assertion-Based Microarchitecture Design for Improved Reliability. ICCD 2006
25EEKiran Seth, Aravindh Anantaraman, Frank Mueller, Eric Rotenberg: FAST: Frequency-aware static timing analysis. ACM Trans. Embedded Comput. Syst. 5(1): 200-224 (2006)
2005
24EEAli El-Haj-Mahmoud, Ahmed S. Al-Zawawi, Aravindh Anantaraman, Eric Rotenberg: Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing. CASES 2005: 213-224
23EERavi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Rotenberg: Tapping ZettaRAMTM for Low-Power Memory Systems. HPCA 2005: 83-94
2004
22EEAli El-Haj-Mahmoud, Eric Rotenberg: Safely exploiting multithreaded processors to tolerate memory latency in real-time systems. CASES 2004: 2-13
21EEAravindh Anantaraman, Kiran Seth, Eric Rotenberg, Frank Mueller: Enforcing Safety of Real-Time Schedules on Contemporary Processors Using a Virtual Simple Architecture (VISA). RTSS 2004: 114-125
20EEJinson Koppanalil, Eric Rotenberg: A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors. IEEE Trans. Computers 53(4): 399-413 (2004)
2003
19EEKhaled Z. Ibrahim, Gregory T. Byrd, Eric Rotenberg: Slipstream Execution Mode for CMP-Based Multiprocessors. HPCA 2003: 179-190
18EEAravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller: Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems. ISCA 2003: 350-361
17EEKiran Seth, Aravindh Anantaraman, Frank Mueller, Eric Rotenberg: FAST: Frequency-Aware Static Timing Analysis. RTSS 2003: 40-51
16EEHuiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte: Adaptive mode control: A static-power-efficient cache design. ACM Trans. Embedded Comput. Syst. 2(3): 347-372 (2003)
2002
15EEJinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg: A case for dynamic pipeline scaling. CASES 2002: 1-8
14EEAlvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan: A Large, Fast Instruction Window for Tolerating Cache Misses. ISCA 2002: 59-70
2001
13EEHuiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte: Adaptive Mode Control: A Static-Power-Efficient Cache Design. IEEE PACT 2001: 61-
12EEEric Rotenberg: Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems. MICRO 2001: 28-39
2000
11EEKarthik Sundaramoorthy, Zachary Purser, Eric Rotenberg: Slipstream Processors: Improving both Performance and Fault Tolerance. ASPLOS 2000: 257-268
10EEZachary Purser, Karthik Sundaramoorthy, Eric Rotenberg: A study of slipstream processors. MICRO 2000: 269-280
9EEEric Rotenberg, James E. Smith: Control Independence in Trace Processors. J. Instruction-Level Parallelism 2: (2000)
1999
8EEEric Rotenberg: AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. FTCS 1999: 84-91
7EEEric Rotenberg, Quinn Jacobson, James E. Smith: A Study of Control Independence in Superscalar Processors. HPCA 1999: 115-124
6EEEric Rotenberg, James E. Smith: Control Independence in Trace Processors. MICRO 1999: 4-15
5EEEric Rotenberg, Steve Bennett, James E. Smith: A Trace Cache Microarchitecture and Evaluation. IEEE Trans. Computers 48(2): 111-120 (1999)
1997
4EEEric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith: Trace Processors. MICRO 1997: 138-148
3EEQuinn Jacobson, Eric Rotenberg, James E. Smith: Path-Based Next Trace Prediction. MICRO 1997: 14-23
1996
2EEErik Jacobsen, Eric Rotenberg, James E. Smith: Assigning Confidence to Conditional Branch Predictions. MICRO 1996: 142-152
1EEEric Rotenberg, Steve Bennett, James E. Smith: Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. MICRO 1996: 24-35

Coauthor Index

1Haitham Akkary [30]
2Ahmed S. Al-Zawawi [23] [24] [26] [29] [30]
3Aravindh Anantaraman [17] [18] [21] [24] [25]
4Steve Bennett [1] [5]
5Gregory T. Byrd [19]
6Thomas M. Conte [13] [16]
7Sameer Desai [15]
8Ali El-Haj-Mahmoud [22] [24]
9Stephen Herr [27]
10Khaled Z. Ibrahim [19]
11Erik Jacobsen [2]
12Quinn Jacobson [3] [4] [7]
13Jinson Koppanalil [14] [15] [20]
14Alvin R. Lebeck [14]
15Tong Li [14]
16Frank Mueller [17] [18] [21] [25]
17Hashem Hashemi Najaf-abadi [32] [34]
18Sailashri Parthasarathy [28]
19Kaustubh Patil [18]
20Jaidev P. Patwardhan [14]
21Zachary Purser [10] [11]
22Prakash Ramrakhyani [15]
23Vimal K. Reddy [26] [28] [30] [31] [33]
24Yiannakis Sazeides [4]
25Kiran Seth [17] [18] [21] [25]
26Krishnan Sivasubramanian [29]
27James E. Smith [1] [2] [3] [4] [5] [6] [7] [9]
28Karthik Sundaramoorthy [10] [11]
29Mark C. Toburen [13] [16]
30Anu Vaidyanathan [15]
31Ravi K. Venkatesan [23] [27] [29]
32Huiyang Zhou [13] [16]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)