2009 |
34 | EE | Hashem Hashemi Najaf-abadi,
Eric Rotenberg:
Architectural Contesting.
HPCA 2009: 189-200 |
2008 |
33 | EE | Vimal K. Reddy,
Eric Rotenberg:
Coverage of a microarchitecture-level fault check regimen in a superscalar processor.
DSN 2008: 1-10 |
32 | EE | Hashem Hashemi Najaf-abadi,
Eric Rotenberg:
Configurational Workload Characterization.
ISPASS 2008: 147-156 |
2007 |
31 | EE | Vimal K. Reddy,
Eric Rotenberg:
Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance.
DSN 2007: 307-316 |
30 | EE | Ahmed S. Al-Zawawi,
Vimal K. Reddy,
Eric Rotenberg,
Haitham Akkary:
Transparent control independence (TCI).
ISCA 2007: 448-459 |
29 | EE | Ravi K. Venkatesan,
Ahmed S. Al-Zawawi,
Krishnan Sivasubramanian,
Eric Rotenberg:
ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling.
IEEE Trans. Computers 56(2): 147-160 (2007) |
2006 |
28 | EE | Vimal K. Reddy,
Eric Rotenberg,
Sailashri Parthasarathy:
Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance.
ASPLOS 2006: 83-94 |
27 | EE | Ravi K. Venkatesan,
Stephen Herr,
Eric Rotenberg:
Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM.
HPCA 2006: 155-165 |
26 | EE | Vimal K. Reddy,
Eric Rotenberg,
Ahmed S. Al-Zawawi:
Assertion-Based Microarchitecture Design for Improved Reliability.
ICCD 2006 |
25 | EE | Kiran Seth,
Aravindh Anantaraman,
Frank Mueller,
Eric Rotenberg:
FAST: Frequency-aware static timing analysis.
ACM Trans. Embedded Comput. Syst. 5(1): 200-224 (2006) |
2005 |
24 | EE | Ali El-Haj-Mahmoud,
Ahmed S. Al-Zawawi,
Aravindh Anantaraman,
Eric Rotenberg:
Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing.
CASES 2005: 213-224 |
23 | EE | Ravi K. Venkatesan,
Ahmed S. Al-Zawawi,
Eric Rotenberg:
Tapping ZettaRAMTM for Low-Power Memory Systems.
HPCA 2005: 83-94 |
2004 |
22 | EE | Ali El-Haj-Mahmoud,
Eric Rotenberg:
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems.
CASES 2004: 2-13 |
21 | EE | Aravindh Anantaraman,
Kiran Seth,
Eric Rotenberg,
Frank Mueller:
Enforcing Safety of Real-Time Schedules on Contemporary Processors Using a Virtual Simple Architecture (VISA).
RTSS 2004: 114-125 |
20 | EE | Jinson Koppanalil,
Eric Rotenberg:
A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors.
IEEE Trans. Computers 53(4): 399-413 (2004) |
2003 |
19 | EE | Khaled Z. Ibrahim,
Gregory T. Byrd,
Eric Rotenberg:
Slipstream Execution Mode for CMP-Based Multiprocessors.
HPCA 2003: 179-190 |
18 | EE | Aravindh Anantaraman,
Kiran Seth,
Kaustubh Patil,
Eric Rotenberg,
Frank Mueller:
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems.
ISCA 2003: 350-361 |
17 | EE | Kiran Seth,
Aravindh Anantaraman,
Frank Mueller,
Eric Rotenberg:
FAST: Frequency-Aware Static Timing Analysis.
RTSS 2003: 40-51 |
16 | EE | Huiyang Zhou,
Mark C. Toburen,
Eric Rotenberg,
Thomas M. Conte:
Adaptive mode control: A static-power-efficient cache design.
ACM Trans. Embedded Comput. Syst. 2(3): 347-372 (2003) |
2002 |
15 | EE | Jinson Koppanalil,
Prakash Ramrakhyani,
Sameer Desai,
Anu Vaidyanathan,
Eric Rotenberg:
A case for dynamic pipeline scaling.
CASES 2002: 1-8 |
14 | EE | Alvin R. Lebeck,
Tong Li,
Eric Rotenberg,
Jinson Koppanalil,
Jaidev P. Patwardhan:
A Large, Fast Instruction Window for Tolerating Cache Misses.
ISCA 2002: 59-70 |
2001 |
13 | EE | Huiyang Zhou,
Mark C. Toburen,
Eric Rotenberg,
Thomas M. Conte:
Adaptive Mode Control: A Static-Power-Efficient Cache Design.
IEEE PACT 2001: 61- |
12 | EE | Eric Rotenberg:
Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems.
MICRO 2001: 28-39 |
2000 |
11 | EE | Karthik Sundaramoorthy,
Zachary Purser,
Eric Rotenberg:
Slipstream Processors: Improving both Performance and Fault Tolerance.
ASPLOS 2000: 257-268 |
10 | EE | Zachary Purser,
Karthik Sundaramoorthy,
Eric Rotenberg:
A study of slipstream processors.
MICRO 2000: 269-280 |
9 | EE | Eric Rotenberg,
James E. Smith:
Control Independence in Trace Processors.
J. Instruction-Level Parallelism 2: (2000) |
1999 |
8 | EE | Eric Rotenberg:
AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors.
FTCS 1999: 84-91 |
7 | EE | Eric Rotenberg,
Quinn Jacobson,
James E. Smith:
A Study of Control Independence in Superscalar Processors.
HPCA 1999: 115-124 |
6 | EE | Eric Rotenberg,
James E. Smith:
Control Independence in Trace Processors.
MICRO 1999: 4-15 |
5 | EE | Eric Rotenberg,
Steve Bennett,
James E. Smith:
A Trace Cache Microarchitecture and Evaluation.
IEEE Trans. Computers 48(2): 111-120 (1999) |
1997 |
4 | EE | Eric Rotenberg,
Quinn Jacobson,
Yiannakis Sazeides,
James E. Smith:
Trace Processors.
MICRO 1997: 138-148 |
3 | EE | Quinn Jacobson,
Eric Rotenberg,
James E. Smith:
Path-Based Next Trace Prediction.
MICRO 1997: 14-23 |
1996 |
2 | EE | Erik Jacobsen,
Eric Rotenberg,
James E. Smith:
Assigning Confidence to Conditional Branch Predictions.
MICRO 1996: 142-152 |
1 | EE | Eric Rotenberg,
Steve Bennett,
James E. Smith:
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching.
MICRO 1996: 24-35 |